RAKESH E.R
Member level 2
Dear sir,
i have only 2 clocks in my project those are System_Clock and SCK_s, those two can i control by using this declarations written below? what are the other things that i have to add before creating the protocol? i am not getting any error instead its accepting all the signals which i have given but none of the violations are solving..
set_dft_signal -view exist -type ScanClock -timing {45 55} -port System_Clock
set_dft_signal -view exist -type ScanClock -timing {45 55} -port SCK_s
Even after defining these 2clocks i get violatons below:
-----------------------------------------------------------------
Begin Pre-DFT violations...
-----------------------------------------------------------------
Warning: Clock input CK of DFF u97_interface_mux_cntrl/u7_interface_top/u0_ahb_apb_bridge1_top/u1_DW_apb_timers_top/U_tim1_timer_reg_8_ was not controlled. (D1-1)
Information: There are 503 other cells with the same violation. (TEST-171)
Warning: Set input SN of DFF u97_interface_mux_cntrl/u7_interface_top/u0_ahb_apb_bridge1_top/u0_DW_apb_top/U_DW_apb_ahbsif_hready_resp_reg was not controlled. (D2-1)
Information: There are 1309 other cells with the same violation. (TEST-171)
Warning: Reset input RN of DFF u97_interface_mux_cntrl/u7_interface_top/u0_ahb_apb_bridge1_top/u0_DW_apb_top/U_DW_apb_ahbsif_pwdata_int_reg_29_ was not controlled. (D3-1)
Information: There are 19405 other cells with the same violation. (TEST-171)
Warning: Clock System_Reset connects to data input (D) of DFF u97_interface_mux_cntrl/u7_interface_top/u2_i2c_spi_ahb_master/u2_ss_spi_top/inst_src_sync_spi_rx/data_reg_reg_60_. (D10-1)
Information: There are 63 other cells with the same violation. (TEST-171)
Warning: Clock System_Clock connects to clock and data inputs (CK/D) of DFF u97_interface_mux_cntrl/u7_interface_top/u0_ahb_apb_bridge1_top/u4_DW_apb_rtc_top/U_DW_apb_rtc_ic_U_DW_apb_rtc_write_sync0_rtc_clk_sync1_reg. (D11-1)
Information: There are 4 other cells with the same violation. (TEST-171)
Warning: Clock System_Reset connects to clock/clock inputs (SN/RN) of DFF u97_interface_mux_cntrl/u7_interface_top/u1_ahb_apb_bridge2_top/u4_apb_keypad_top/i_apb_keypad_timer/tick_divider_reg_16_. (D12-1)
Information: There are 19 other cells with the same violation. (TEST-171)
Warning: System_Reset clock path affected by new capture on LS input RN of DFF u97_interface_mux_cntrl/u7_interface_top/u0_ahb_apb_bridge1_top/u0_DW_apb_top/U_DW_apb_ahbsif_pwdata_int_reg_29_. (D15-1)
Source of violation: input RN of DFF u97_interface_mux_cntrl/u7_interface_top/u1_ahb_apb_bridge2_top/u7_tron_glue_logic_top/s_reset_reg_reg_0_.
Information: There are 20127 other cells with the same violation. (TEST-171)
Warning: Bus gate u97_interface_mux_cntrl/u7_interface_top/u1_ahb_apb_bridge2_top/u5_TRON_DAC/DAC_AOUT_0 failed contention ability check for drivers u_ioring_dac/pad_bottom_DAC_AOUT_0 and u97_interface_mux_cntrl/u7_interface_top/u1_ahb_apb_bridge2_top/u5_TRON_DAC/u_dac_0. (D20-1)
Information: There are 7 other cells with the same violation. (TEST-171)
---------------------------------------------------------------
DRC Report
Total violations: 41687
-----------------------------------------------------------------
67 MODELING VIOLATIONS
67 Cell has unknown model violations (TEST-451)
152 TOPOLOGY VIOLATIONS
90 Improperly driven three-state net violations (TEST-115)
62 Unconnected input pin violations (TEST-332)
41468 PRE-DFT VIOLATIONS
504 Uncontrollable clock input of flip-flop violations (D1)
1310 DFF set/reset line not controlled violations (D2)
19406 DFF set/reset line not controlled violations (D3)
64 Clock feeding data input violations (D10)
5 Clock feeding both clock and data input violations (D11)
20 Clock feeding multiple clock/set/reset inputs violations (D12)
20148 Clock path affected by clock captured by clock in level sensitive clock_port violations (D15)
11 Bus gate capable of contention violations (D20)
i am very new to dft field and a fresher too in professional field.. i am not able to understand what else i have to write in scripts other than this two lines to clear the violations..can you please help me to resolve this..? if you need any more information about my question i can give you..
Regards,
Rakesh
i have only 2 clocks in my project those are System_Clock and SCK_s, those two can i control by using this declarations written below? what are the other things that i have to add before creating the protocol? i am not getting any error instead its accepting all the signals which i have given but none of the violations are solving..
set_dft_signal -view exist -type ScanClock -timing {45 55} -port System_Clock
set_dft_signal -view exist -type ScanClock -timing {45 55} -port SCK_s
Even after defining these 2clocks i get violatons below:
-----------------------------------------------------------------
Begin Pre-DFT violations...
-----------------------------------------------------------------
Warning: Clock input CK of DFF u97_interface_mux_cntrl/u7_interface_top/u0_ahb_apb_bridge1_top/u1_DW_apb_timers_top/U_tim1_timer_reg_8_ was not controlled. (D1-1)
Information: There are 503 other cells with the same violation. (TEST-171)
Warning: Set input SN of DFF u97_interface_mux_cntrl/u7_interface_top/u0_ahb_apb_bridge1_top/u0_DW_apb_top/U_DW_apb_ahbsif_hready_resp_reg was not controlled. (D2-1)
Information: There are 1309 other cells with the same violation. (TEST-171)
Warning: Reset input RN of DFF u97_interface_mux_cntrl/u7_interface_top/u0_ahb_apb_bridge1_top/u0_DW_apb_top/U_DW_apb_ahbsif_pwdata_int_reg_29_ was not controlled. (D3-1)
Information: There are 19405 other cells with the same violation. (TEST-171)
Warning: Clock System_Reset connects to data input (D) of DFF u97_interface_mux_cntrl/u7_interface_top/u2_i2c_spi_ahb_master/u2_ss_spi_top/inst_src_sync_spi_rx/data_reg_reg_60_. (D10-1)
Information: There are 63 other cells with the same violation. (TEST-171)
Warning: Clock System_Clock connects to clock and data inputs (CK/D) of DFF u97_interface_mux_cntrl/u7_interface_top/u0_ahb_apb_bridge1_top/u4_DW_apb_rtc_top/U_DW_apb_rtc_ic_U_DW_apb_rtc_write_sync0_rtc_clk_sync1_reg. (D11-1)
Information: There are 4 other cells with the same violation. (TEST-171)
Warning: Clock System_Reset connects to clock/clock inputs (SN/RN) of DFF u97_interface_mux_cntrl/u7_interface_top/u1_ahb_apb_bridge2_top/u4_apb_keypad_top/i_apb_keypad_timer/tick_divider_reg_16_. (D12-1)
Information: There are 19 other cells with the same violation. (TEST-171)
Warning: System_Reset clock path affected by new capture on LS input RN of DFF u97_interface_mux_cntrl/u7_interface_top/u0_ahb_apb_bridge1_top/u0_DW_apb_top/U_DW_apb_ahbsif_pwdata_int_reg_29_. (D15-1)
Source of violation: input RN of DFF u97_interface_mux_cntrl/u7_interface_top/u1_ahb_apb_bridge2_top/u7_tron_glue_logic_top/s_reset_reg_reg_0_.
Information: There are 20127 other cells with the same violation. (TEST-171)
Warning: Bus gate u97_interface_mux_cntrl/u7_interface_top/u1_ahb_apb_bridge2_top/u5_TRON_DAC/DAC_AOUT_0 failed contention ability check for drivers u_ioring_dac/pad_bottom_DAC_AOUT_0 and u97_interface_mux_cntrl/u7_interface_top/u1_ahb_apb_bridge2_top/u5_TRON_DAC/u_dac_0. (D20-1)
Information: There are 7 other cells with the same violation. (TEST-171)
---------------------------------------------------------------
DRC Report
Total violations: 41687
-----------------------------------------------------------------
67 MODELING VIOLATIONS
67 Cell has unknown model violations (TEST-451)
152 TOPOLOGY VIOLATIONS
90 Improperly driven three-state net violations (TEST-115)
62 Unconnected input pin violations (TEST-332)
41468 PRE-DFT VIOLATIONS
504 Uncontrollable clock input of flip-flop violations (D1)
1310 DFF set/reset line not controlled violations (D2)
19406 DFF set/reset line not controlled violations (D3)
64 Clock feeding data input violations (D10)
5 Clock feeding both clock and data input violations (D11)
20 Clock feeding multiple clock/set/reset inputs violations (D12)
20148 Clock path affected by clock captured by clock in level sensitive clock_port violations (D15)
11 Bus gate capable of contention violations (D20)
i am very new to dft field and a fresher too in professional field.. i am not able to understand what else i have to write in scripts other than this two lines to clear the violations..can you please help me to resolve this..? if you need any more information about my question i can give you..
Regards,
Rakesh
