how to choose the optimum gate length for the switch

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lijulia

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transistor in the switch-cap bank of wide-band vco? if I use .5um siGe process.

This optimum length is based on the tuning range and operating frequency, why?
 

Are you talking about the switches which switch in and out some caps.

In that case, remember that the cap (Cgd) pf these switches will add onto your caps and cause a loss in frequency. Also, you want low R which means low L.

Hence a trade-off
 

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