how to choose cmos device size and bias for digital circuits?

[mona123]

How would one go about deciding what CMOS device size and bias current to choose for designing digital circuits? Thanks.

 

[jimway]

What do you mean by biasing the digital circuits? If you ment the cml logic, the swing, and common mode voltage will define the tail current.

 

[mona123]

yes for biasing thats what would make sense..but i dont know whats the right way to choose device size given a choice of both w and l for cmos? any book that desribes this well.

 

[kgl_13gr]

You would usually go with picking the smallest width for the NMOS that the technology allows or a typical transistor is characterized at. Then you make the PMOS 2-3 times wider to account for the difference in mobilities. This would be a unity gate. After that you scale these dimensions up according to the load you have to drive from each gate. Googling for Logical Effort will give you more information on how you could do that systematically.

 

[john blue]

If its unity, the CMOS device would be symmetrical which gives the advantages of full voltage swing as well as low power consumption. But, on the other hand, the transistors required is more compared to fully NMOS implementation

 

[mona123]

What about length, would you always go for minimum length for nmos as well as pmos or could it be different?

 

[john blue]

Yes, NMOS should always be minimum length constrained by the fabrication technology. Since the difference in mobility of electrons and holes, PMOS has to be 2 to 3 times NMOS.

 

[kgl_13gr]

You don't have any reason to go for non-minimum length, as this degrades speed.

 

[mona123]

Is there any situation when you consider different lengths for nmos and pmos? Is there any situation when you would like to go away from minimum length?

 

[john blue]

PMOS length is always 2 to 3 times NMOS. Why would you want to go away with minimum length? Minimum length will make your device smaller as long as we have the technology to do them.

 

[mona123]

Thats what I want to know, if i have voltage to operate can i choose larger length so that Vt variation is less over process, or Ro is larger, or anything else? does minimum channel length give me advantage then?

 

[john blue]

You can always play around with the doping concentration?

 

[mona123]

what does doping concentration got to do with circuit analysis for a given technology node?