How to choose Bipolar sizes in BiCMOS design?

Hi,

I'm new to BiCMOS designs (BJT in particular). In CMOS, we choose WL accordingly to obtain the gm we want etc. What about BJT? The main parameter to vary is emitter area, but this only affects Is variable in the Ic equation. What are the considerations is choosing a good size during designs?

What are the side effects if Ic is too high for a small BJT?

Any rules of thumb?

Usual practice for bipolar design - you have several fixed device layouts and spice model for every layout. That is because layout change may change some parameters of Spice model. And this can change not only Is but Rb, Rc or others also.
So If you need larger transistor size better to use several fixed-layout devices connected in parallel. It is also good practice when you need keep ratio for current mirrors.
If you need high-current devices (more than several hundred mA) you should use so called ballast resistors connected to emitter or base.
The gain (B or h21e) of bipolar transistor has dependence on Ic. It is lowered both with low Ic and high Ic and has maximum for some middle Ic.
The device current density (or device size) should correspond to the Ic when gain has the max value.
Good luck,
Fom

just to add to what has already been said. Usually, the Ft of the transistor has a maximum for Ic slightly before h21 starts falling (at the higher current end). So, to choose the device area, take a transistor that can conduct the needed Ic with good h21 and which gives good Ft (if you need it).

usually in bicmos processes, the process has been highly optimized for cmos, and the bjt's are "scrap" devices. if you have npn & lateral pnp, this is the case.

anyway, these processes almost always have a suggested npn layout, it is not like bipolar where you can draw the emitters any size you want. also, in bicmos, the bipolars are so big (compared to cmos) that they are only used for special things - input pair of a low-offset amp, bandgap, temp sensor. these applications all use the bjt's in the "signal" region - 1 to 100uA, of which single bjt's are fine to use. bandgap of course uses 1:8, etc. in no cases have i seen a power bjt in a bicmos process..

what's your application? you should be considering whether a bjt is the right device for you if you are asking it to carry large currents. there is probably a better (smaller) way using mos.

I will allow myself to strongly disagree that the bicmos processes have scrappy bjts. I'm currently working with 0.35u SiGe bicmos and have to tell you that we have both vertical npn and pnp with about 40Ghz Ft for the npn.
Also, bjts we use almost everywhere on par with the cmos. Many times they prove to be very useful.

I do agree with sutapanaki
Currently I am using 0.35um SIGE. The Foundry provides high perfomance npn whose ft is up to 40GHZ.

But I have a headache problem, for a specific npn. If I only have a current budget of about 100uA for each emitter follower and differential pair. I would choose a tiny device and bias it at the highest ft. But the problem arises here, the tiny device has a huge mismatch and offset parameter. How do I solve this problem?

I think u can use a typical size of the foundry.just as Unitrode company.they use even times of the two bipolars to build a two-transistor bandgap.

chihyang wang said:

I do agree with sutapanaki
Currently I am using 0.35um SIGE. The Foundry provides high perfomance npn whose ft is up to 40GHZ.

But I have a headache problem, for a specific npn. If I only have a current budget of about 100uA for each emitter follower and differential pair. I would choose a tiny device and bias it at the highest ft. But the problem arises here, the tiny device has a huge mismatch and offset parameter. How do I solve this problem?

Click to expand...

Are you using a austriamicrosystem process?

hehe - you can strongly disagree if you want.

remember, i mentioned a process containing lateral pnp - this is a sure sign that your bjt's are scrap. vertical pnp's mean the process is at least targeted to bjt if not derived from a bipolar process, and obviously, the point of a sige process is to make hbt so i would really hope they have a good bipolar!

i personally think there are too many cellphones in the world already, so i guess i don't even think about you poor rf guys when i think bicmos, but i'll keep it in mind in the future..

Building a lateral pnp is not a rocket science, you know. Even pure CMOS has them. As a matter of fact the bicmos process I use has lateral pnp too, but this fact alone doesn't make it a scrappy proces.
Oh, and BTW, I'm not an rf guy, but still use bicmos. RF is not the only thing that can benefit from it.

for bjt and hbt dimensioning for optimised design please check TRADICA tool vis this two links:

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