1) In DC do the following:
list_libs
Based on output above, locate the library name, should be on the same line as your library file name. Then do:
report_lib lib_name (example: report_lib class)
This will give some basic info on the procees used. For detail process information. you should refer to the library data book.
2) Yes. You should use the wire load models that are available in your target_lib (or in some cases from your link libraries). If you are synthesizing a design for say, TSMC 0.25u, then you must use the wire load models in the library provided by TSMC for the 0.25u process. You should not use a wire load model from some other process or foundary.
3) WLM are technology dependent. However the accuracy drops for 0.18u and below. Generally there are two ways to use WLM:
a) Manually - you select A wire load from the list available from your library. Generally WLM are developed based on area. What we normally do is, take a design, do a quick synthesis (no constraints), just get the gate-count (area), and based on that, we choose the WLM for our actual run.
b) Let DC choose. If your lib have the auto WLM table, DC will choose one for you.
Bottom line: do some research on your WLM to see if its optimistic or pessimistic. If its optimistic - just overconstrain your design, about 10% to account for any errors.