I am attaching the simulation file of one of my circuit.It consists of many opamps and BJT's. I know how to check the stability of this circuit(I know it for single opamp circuits).
My input is V3(I_PT100_SET) and output is I_PT100_ACT .
I can see some ringing initially at output .
Can you please help me to check the stability and to compensate it.
I am attaching the simulation file of one of my circuit.It consists of many opamps and BJT's. I know how to check the stability of this circuit(I know it for single opamp circuits).
My input is V3(I_PT100_SET) and output is I_PT100_ACT .
I can see some ringing initially at output .
Can you please help me to check the stability and to compensate it.
Your rar file opened fine in 7zip.
I don't see any design specs. You must have them.
I added test nodes on each output and squeezed the schematic and changed input to a square wave.
some comments to your circuit:
* missing power supply decoupling capacitors. Yes, I know the simulation does without it. It - unrealistically - treats the supplies as ideal. The problem is that they simply get forgotten when doing the real circuit.
* you say PT100, but there is no PT100 ...
* You use the INA U8 at resistor R14 referenced to GND. I see no use of an INA here. A simple OPAMP will do.
* On the other hand you use OPAMPs on R13 .. with two non_GND signals. Here a INA would be preferred.
* also the OPAMP_made_INA .. has the high gain at the output_OPAMP, where it is beneficial to have it at the input OPAMPs
* with your two measurement paths you measure the voltage drop across two resistors in series. I don´t understand it´s purpose, since I expect both measurment paths to show identical signals (maybe with different gain)
* You say PT100 .. which is a temperature sensor. It´s respons is in the low Hz (at best case). But your whole measurement is designed for much higher frequency. I usually expect low pass filters to get rid of high frequency (above PT100 response)
* but indeed I don´t understand the purpose of the square wave input at all (since they will influence stabilty a lot)
Thus my idea is to FIRST place low pass filtering capacitors ... and then look for stability.
1. To answer the initial question how to check stability. Best way is loop gain analysis. Alternatively small step excitation around operation point.
Obviously left part of the circuit is intended as PT100 current source. It will be normally operated with fixed setpoint, applying a ramp from 0 to 3,3 V (corresponds to about 0 to 20 mA output current) doesn't seem to serve a purpose.
2. The current source circuit is overly complicated and involving possible latch-up issues, because OP common mode range can be exceeded if Q2 is turned fully on. A single OP current source can achieve same or better perfoemance.
3. I checked stability for 1, 5 and 20 mA. According to bode plot, circuit is stable with 45° phase margin at 20 mA. See .zip for simulation setup with loop gain measurement.
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Simple OP current source, output current up to 10 mA with ADA4077.
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LTspice has apparently DC convergence problem with ADA4077 OP model, set .options noopiter.
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For higher output currents, you can use boost transistor
See derivation of current source dimensioning in appended .pdf.
* You say PT100 .. which is a temperature sensor. It´s respons is in the low Hz (at best case). But your whole measurement is designed for much higher frequency. I usually expect low pass filters to get rid of high frequency (above PT100 response)
Obviously left part of the circuit is intended as PT100 current source. It will be normally operated with fixed setpoint, applying a ramp from 0 to 3,3 V (corresponds to about 0 to 20 mA output current) doesn't seem to serve a purpose.
There are several issues; Bode Plots are useless, if there are gross failures. A small-step response is best.
1. U1 cannot drive 1k without a load regulation error and it is unstable with high R values at unity gain. Using -/+1mV in 0.02 mV out.
ADA4077 does not work well here with unlimited BW and weird excessive crosstalk between the dual Op Amps above GBW from two cascaded inverters using a 1us risetime step.
Action: Use a better OA with better drive current & stability with low Vio. Alternative: Eliminate U1 and swap U8 inputs to correct the polarity. Below is a 2 mV input step -1mV to +1mV with 1us rise time
I don't see that any of the issues addressed in above post applies to the given circuit. It's a DC current source and doesn't need dynamical performance, except for stability.
As said, I don´t understand the whole function.
Bascially I place LPF capacitors at every amplifier to limit the bandwith. This helps to reduce noise. Usually it also reduces noise and ringing and improves overall stability.
You can (should) ask yourself for every amplifier: "What is the maximium frequency at the output I´m interested in?"
the "whole" ... so not only the left part?
May I ask what you are trying to achieve with the whole circuit .. or better say the whole application?
What is the regulation loop? Is the DAC involved in the loop?
1. U1 cannot drive 1k without a load regulation error and it is unstable with high R values at unity gain. Using -/+1mV in 0.02 mV out.
ADA4077 does not work well here with unlimited BW and weird excessive crosstalk between the dual Op Amps above GBW from two cascaded inverters using a 1us risetime step.
If you don't mind could you please expalin more about it.I did not understand completely
The opamp output current capacity is ±10.
I changed the value of R3,R4,R8 from 1K to 10K and it is working now
I don't see that any of the issues addressed in above post applies to the given circuit. It's a DC current source and doesn't need dynamical performance, except for stability.
The load capacitance for the max slew rate of current causes increasing overshoot, which is a sign of loss of stability, phase margin.
1K load with a large step voltage likewise causes a longer settling time and more ringing than 10k.
The only evidence I found in the datasheet was at 2k load overshoot plots which you normally don't see on bipolar Op Amps, except for 1 or two load examples.
These followed my simulated results and previous comments about load regulation stability being unusual.
The discussed circuit is unconditionally stable. Dynamic requirements, e.g. xx degree phase margin, maximal yy percent overshoot haven't been yet specified. Circuit application Pt100 current source doesn't involve particular dynamic requirements. Thus I assume so far that a few percent overshoot as seen in the simulation are not an issue.
Other Parts Discussed in Post: OPA211 SPICE is a useful tool to help check for potential circuit stability problems. Here is one simple way to do it: Figure...
The transient response of a negative-feedback amplifier can help us to understand the nature of stability and convey useful information about the stability characteristics of a particular circuit.
www.allaboutcircuits.com
A way of confirming on bench with simple tools. Note for second order (typically) or
higher order with dominant poles.
If stability was a binary question it is 0 or 1 oscillating or not, this is true.
But normally I use the words "unstable" in the analog margin domain such as margin for phase, overshoot or settling time. It all depends on the context of the use for me and the requirements of the application. I meant no confusion but there is a difference in settling time with loading from my quick simulation.
Yes, settling time can be toughest to achieve, the "sweet spot" must be found if you're being appropriately challenged.
I like impulse / step response in transient analysis as the "triage pass". Put "bump sources" on every "input" (incl rails) and hit one at a time, recognize the damping signature, chase the ugly down its hole.