how to check the functionality between cdl and verilog RTL ?

[yusq]

the circuit guys design the circuit according to the spec. on the other hand, front guys write the RTL code according to the spec. how can you verify they function the same. You know simulation is not a good way because you have to take a great effort to compare the two result between the verilog simulation output and hspice simulation output.

 

[blacklancer]

i think formal verification is a good way

 

[CatKing]

Verplex LEC can do it exactly

 

[avin11]

Re: how to check the functionality between cdl and verilog R

Whats formal verification ?

 

[yusq]

i know CONFORMAL LEC, however, when you use lec to extract a large circult, it is very difficult to debug. The lec will generate some logic such as the ff with set & reset tie to 0 etc...

 

[flypig]

i know sysn opsys has the tool, Formality, which can verify the netlist and verilog RTL.

 

[farmerwang]

Re: how to check the functionality between cdl and verilog R

Use verplex(now Cadence), Conformal LEC

 

[Memphis]

Re: how to check the functionality between cdl and verilog R

A far as I know the formail verification tool like lec now just work between RTL and gate level netlist now. If you want to compare between spice netlist and rtl, you should need the translation tool like blacktie of verplex to perform the translation from spice netlist to gate level netlist in order to to the formal verification. Please tell me if anything wrong, thanks a lot... :wink:

 

[gerade]

Re: how to check the functionality between cdl and verilog R

formality from syn0psy, cve from infineon

 

[albertyin]

If you can dump verilog netlist from your schematic, you can go formal verification.
If you only have CDL (why not spice?), you need to make script program to convert CDL to verilog format, but in the converted verilog netlist, all ports have to be set as inout.