chris_li
Member level 2
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Hi Guys, below is a portion snapshot of sub-block layout from P&R tool. Stdcell places back-to-back in each cellrow and power/gnd rail alternative supply stdcell.
For each power/gnd rail, VDD and VSS pin generated at the line end as illustrated left side, which is used to connect power/gnd net at top-level.
When run LVS by Calibre, those VDD and VSS extracted as separated ports, thus port number is not matching source's (note: source only has tow powre/gnd ports: VDD and VSS)
So, how to have Calibre identify rail pin "VDD" and "VSS" as only two ports?
![lvs.png lvs.png](https://www.edaboard.com/data/attachments/7/7899-3fb839f60b36aa6bded24b7cc4099811.jpg)
For each power/gnd rail, VDD and VSS pin generated at the line end as illustrated left side, which is used to connect power/gnd net at top-level.
When run LVS by Calibre, those VDD and VSS extracted as separated ports, thus port number is not matching source's (note: source only has tow powre/gnd ports: VDD and VSS)
So, how to have Calibre identify rail pin "VDD" and "VSS" as only two ports?
![lvs.png lvs.png](https://www.edaboard.com/data/attachments/7/7899-3fb839f60b36aa6bded24b7cc4099811.jpg)