How to change the threshold of voltage difference between source and drain when the gate voltage is zero

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henry kissinger

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The NMOS configuration is as below.
the gate voltage is 0 V
the source voltage is fixed to 0 V, the drain voltage is swept from -2 V to 2V.
We can see that the threshold of voltage difference between source and drain is very little, at drain voltage around -0.01 V.
What parameter of this NMOS shown in the second graph (Level1_Model) I can change in order to have the threshold voltage difference much negative, say -10 V ?

 

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What "threshold voltage" are you talking about?
Normally that's the Vgs where the MOSFET just starts to conduct, and that does not vary significantly with a change in drain voltage.
 

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Symmetrical FETs have no dedicated "drain" and "source". The function is switched according to the voltage difference between the channel terminals. In so far your interpretation of results misses the point.

In addition, do you realize that negative "Vd" puts bulk diode in forward bias. You see Vbs rather than Vgs threshold.
 

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