How to capture two consecutive edges of a clock? (Verilog)

KlausST said:

You now use "state" it should work.

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KlausST said:

P1=1 If P1=1 then P2=1

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dirac16 said:

Watch out race condition when P1=1?

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@ poseedge
* if EN = 0 then P1=0, P2=0
Else
{
If P1=1 then P2=1
P1=1
}

KlausST said:

think about two DFF in shift register style:
1--> DFF1 --> DFF2

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dirac16 said:

​

I want to capture the first two consecutive edges of CLK after EN signal goes high. The following picture shows the idea. The thing that matters is that the difference between P1 and P2 must be exactly (up to 2% error is fine) one period of CLK. Since CLK oscillates at 2.4 GHz the difference between P1's and P2's edges should come up 417ps +/- 8ps. For that to happen the path from CLK to P1's output and from CLK to P2's output must be fully symmetric, something that looks hard to be met in practice? There are maybe a few ways to implement the idea but I don't know if there is a concrete solution to the problem. What you see below is my attempt at the solution:

View attachment 173986

Code:

module test(
            input EN,
            input CLK,
            output P1,
            output P2
);

reg [1:0] state;
reg PR1, PR2;

always @(posedge CLK) begin

    if (!EN)
        state <= 0;
    else
        state <= state+1; 

end

always @(state) begin

    case (state)
        2'b01: PR1 <= 1;           
        2'b10: PR2 <= 1;
    endcase

end

assign P1 = PR1;
assign P2 = PR2;

endmodule

The above code though works in pure RTL simulations it may not actually work in practice because of case conditions that may not suggest the same symmetric logic. Do you have an idea better than mine?

​

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Trent_N said:

You can force these 2 Flip Flops to be placed next to each other and you can pre-route the clock to be sure that the both Flip Flops use the same last clock buffer of the clock tree. You will need to do some custom layout tricks.
You will also need to match the load of these 2 Flip Flops, again using custom layout and synthesis methods.
There will be some on chip variation even with identical layout for both of these Flip Flops. On chip variation can be minimized by using the fastest Flip Flops. The clock rising edge should be fast, Flip flops are faster when the clock edge is fast.

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