How to capture two consecutive edges of a clock? (Verilog)

[dirac16]

​

I want to capture the first two consecutive edges of CLK after EN signal goes high. The following picture shows the idea. The thing that matters is that the difference between P1 and P2 must be exactly (up to 2% error is fine) one period of CLK. Since CLK oscillates at 2.4 GHz the difference between P1's and P2's edges should come up 417ps +/- 8ps. For that to happen the path from CLK to P1's output and from CLK to P2's output must be fully symmetric, something that looks hard to be met in practice? There are maybe a few ways to implement the idea but I don't know if there is a concrete solution to the problem. What you see below is my attempt at the solution:

module test(
            input EN,
            input CLK,
            output P1,
            output P2
);

reg [1:0] state;
reg PR1, PR2;

always @(posedge CLK) begin

    if (!EN)
        state <= 0;
    else
        state <= state+1;    

end

always @(state) begin

    case (state)
        2'b01: PR1 <= 1;              
        2'b10: PR2 <= 1;
    endcase

end

assign P1 = PR1;
assign P2 = PR2;

endmodule

The above code though works in pure RTL simulations it may not actually work in practice because of case conditions that may not suggest the same symmetric logic. Do you have an idea better than mine?

​

 

[KlausST]

Hi,

You generate (output) two signals, but with "capture" I rather think about reading in (input) sone signals.

You now use "state" it should work.

You could do it shorter (pseudo code)

@ poseedge
* if EN = 0 then P1=0, P2=0
Else
P1=1
If P1=1 then P2=1

Klaus

 

[dirac16]

You now use "state" it should work.

I know it works but with their relative edges exactly one CLK apart? There is no reason for the synthesizer to make CLK-->P1 and CLK-->P2 paths undergo the same delay. You know the latter may end up being slower or else even though the logic finally generates P1 and P2.

--- Updated Jan 19, 2022 ---

P1=1 If P1=1 then P2=1

Watch out race condition when P1=1?

--- Updated Jan 19, 2022 ---

Or I don't know if I should be care about timings only after synthesis? Because synthesizers have tools that allow you to time paths.

 

[KlausST]

Hi,

Watch out race condition when P1=1?

this is not software where it is processed line by line.
It is hardware. Lines are processed in parallel.

so if P1 was 0 before the clock edge,
then you may set P1=1
but still "IF P1=1" still sees the "0" value before the clock edge.

***
If you what it more "software compatible" then reverse the order:

@ poseedge
* if EN = 0 then P1=0, P2=0
Else
{
If P1=1 then P2=1
P1=1
}

But the result will be the same.

added:
think about two DFF in shift register style:
1--> DFF1 --> DFF2
both DFF are clocked on the same edge
* after the first clock the "1" is at output of DFF1 (= input of DFF2)
* after the second clock edge: the "1" is also on the output of DFF2

Klaus

 

[dirac16]

think about two DFF in shift register style:
1--> DFF1 --> DFF2

Yeah, it's nothing but two DFFs in series. Thank you as always!

 

[Trent_N]

​

I want to capture the first two consecutive edges of CLK after EN signal goes high. The following picture shows the idea. The thing that matters is that the difference between P1 and P2 must be exactly (up to 2% error is fine) one period of CLK. Since CLK oscillates at 2.4 GHz the difference between P1's and P2's edges should come up 417ps +/- 8ps. For that to happen the path from CLK to P1's output and from CLK to P2's output must be fully symmetric, something that looks hard to be met in practice? There are maybe a few ways to implement the idea but I don't know if there is a concrete solution to the problem. What you see below is my attempt at the solution:

View attachment 173986

module test(
            input EN,
            input CLK,
            output P1,
            output P2
);

reg [1:0] state;
reg PR1, PR2;

always @(posedge CLK) begin

    if (!EN)
        state <= 0;
    else
        state <= state+1; 

end

always @(state) begin

    case (state)
        2'b01: PR1 <= 1;           
        2'b10: PR2 <= 1;
    endcase

end

assign P1 = PR1;
assign P2 = PR2;

endmodule

The above code though works in pure RTL simulations it may not actually work in practice because of case conditions that may not suggest the same symmetric logic. Do you have an idea better than mine?

​

You can force these 2 Flip Flops to be placed next to each other and you can pre-route the clock to be sure that the both Flip Flops use the same last clock buffer of the clock tree. You will need to do some custom layout tricks.
You will also need to match the load of these 2 Flip Flops, again using custom layout and synthesis methods.
There will be some on chip variation even with identical layout for both of these Flip Flops. On chip variation can be minimized by using the fastest Flip Flops. The clock rising edge should be fast, Flip flops are faster when the clock edge is fast.

 

[Trent_N]

You can force these 2 Flip Flops to be placed next to each other and you can pre-route the clock to be sure that the both Flip Flops use the same last clock buffer of the clock tree. You will need to do some custom layout tricks.
You will also need to match the load of these 2 Flip Flops, again using custom layout and synthesis methods.
There will be some on chip variation even with identical layout for both of these Flip Flops. On chip variation can be minimized by using the fastest Flip Flops. The clock rising edge should be fast, Flip flops are faster when the clock edge is fast.

Also, 8ps is a small time. You must take care about the clock jitter and the power supply noise. The Flip Flop timing is very sensitive to voltage.
This difficult timing requirement is not common. There could be another method to implement what you need that is easier. How are these 2 signals (P1,P2) used?