How to cancel the internal pole in this circuit

Hi All:

I am designing a low power OTA, in which a local CMFB technique is used to improve the GBW and SR without increasing power too much. The circuit is shown in the attachment.
GBW, and SR has been met by the introducing of two resistors at the top, but these two resitors also increase the second pole of this circuit, as a result the phase margin has been decreased significantly. A paper, "Simple technique using local CMFB to enhance slew rate and bandwidth of one-stage CMOS op-amps", suggests to add one resistor between the op-amp terminal and CL, as shown in my schematic, to provide a zero to cancel this pole. I tried this scheme, but I couldn't see any change. I doubt this resistor will introduce any zero, because it doesn't add another signal path.
If anybody can look into this circuit and give me some suggestions to compensate this second pole. Thanks in advance.

J

Looking at the circuit, differential signal see an impedance of R.,while the common-mode signals see an impedance of 1/gm(gm of M3 and M4). So, this gives you a very good CMRR.,BUT your differential load is still R. So, now what you have is a voltage signal at the output of R driving a common-source amplifier formed by M6. Ofcourse, now you have opened your-self upto Miller effect because in a normal symmetric OTA amplifier, the load is just 1/gm of M3 and M4(very low-impedance) and hence the pole formed by these is really non-dominant. Now te pole is formed by R and the C it is driving which is really Cds of M6 multiplied by gm of M6.
So, chances are, your non-dominant pole became dominant or very close to being dominant!!!. There are 3 things you can do.,all with their own side effects::

* Reduce the value of R. (This will also reduce your differential gain.,so to get back the same gain, you have to increase the current.,)

*Classic miller compensation. Put a Cc, (1pF) cap. between the drain of M7/M6 and the drain of M4. This will not change your DC gain, but your GBW will now be a function of Cc. You might also need to increase your current.,to get the same slew rate.

* I am not sure how low you can make your L., but reduce W*L of M6 while keeping the same W/L. Ideas is to reduce the Cds.

Hope this helps.,,,

From where I look at it, the impedance seen by the drains of the differential pairs is R + 1/gm. I do not think that it matters.

Another thing which is important here is that, at your load, you are taking the output at the midpoint between the resistor R1 and the cap. That effectively is giving only a dominant pole. Why dont you tap the output at the resistor with R and C in series. Kindly come back the results you got. I suppose in that configuration, it will produce some lead compensation.......

This is a classic circuit.,to improve CMRR.,all common-mode signals see 1/gm.,
while the differential signals see R.,it is never R+1/gm in any configuration.,
(Note the shorted fgates.).,so differentially the 1/gms never matter.

the dominant pole should be at the output
second dominant pole is the one mentioned by one of the previous poster

to get a zero, u should tap the output at the left hand side of the resistor. ur connection is alright, but u tapped at the wrong node.

this eff give u a lead lag compensation, one more pole would be introduced, make sure this doesn't get anyway near ur bandwidth.

Added after 1 minutes:

the dominant pole should be at the output
second dominant pole is the one mentioned by one of the previous poster

to get a zero, u should tap the output at the left hand side of the resistor. ur connection is alright, but u tapped at the wrong node.

this eff give u a lead lag compensation, one more pole would be introduced, make sure this doesn't get anyway near ur bandwidth.

Vamsi Mocherla said:

... Another thing which is important here is that, at your load, you are taking the output at the midpoint between the resistor R1 and the cap. That effectively is giving only a dominant pole. Why dont you tap the output at the resistor with R and C in series. Kindly come back the results you got. I suppose in that configuration, it will produce some lead compensation.......

Click to expand...

[quote = "lastdance"]... to get the zero, you should tap your output at the left hand side of the resistor......[/quote]

Thank you everybody, especially Vamsi Mocherla and Lastdance, It works now.
Another thing I am wondering is the impedence seen by the differential pairs should be R//r01//r03?

J

it should be R as pointed out by a previous poster.

the point in b/w the R is a virtual gnd.

Jenifer_gao said:

Another thing I am wondering is the impedence seen by the differential pairs should be R//r01//r03?

J

Click to expand...

You are right for a differential signal the impedance will be R||r01||r03, but assuming R<<r01 or r03 the impedance is roughly R, for a common mode signal the impedance is 1/gm||r01||r03 so roughly 1/gm