How to calualte the capacitor size when design pipeline adc?

[wjxcom]

Hi all: During designing the Pipeline ADC, the capacitor is the key component to the MDAC. So I beg help from this BBS and want to know How to calualte the capacitor size when design pipeline adc?
For example, when I design a 12bits PipelineADc, The capacitor size for the MDAC is selected to be 50fF based on our desired signal-to-noise ratio (SNR) of 70dB.
For a 12-bit ADC, the ideal SNR is SNR=6.02×12+ 1.76=74 dB. Therefore, it seems reasonable to aim for approximately 70dB SNR in our ADC. 70dB SNR correlates to 10^(70/20)=3162, that is, 3162 parts signal for every 1 part noise. The largest input voltage swing on the capacitors is 1V peak. This equates to a 0.35V RMS swing. Therefore, the total RMS noise must be 0.35/3162= 110μ.
If we assume that half of the noise comes from the amplifier, and half from thermal noise, we are able to determine the necessary size of the capacitors. ‘Half’ of the total RMS noise of 110μV is 110μV/√2=77μ RMS. Given that √KT/C=σ, we find that the total C should be at least 700fF. For 31 levels, we need 31 individual capacitors of 22fF. A capacitor size of 50fF is selected because it is the smallest capacitor that can be used in order to obtain sufficient matching

I do not know this way is right or not. beg your help, thanx you!!

 

[JoannesPaulus]

Your calculation is generally correct. Beware of the noise from the sampling switches.
Moreover, you might want to share the noise between thermal and opamp in a slightly different manner since you have a minimum capacitor size limit...

 

[wjxcom]

Re: How to calualte the capacitor size when design pipeline

Hi JoannesPaulus: in fact, I found this calulation method from the thesis "12b 100MSps Pipeline ADC with Open-Loop Residue Amplifier" in page 65, which will be found from the attachment.

There have some questions for me yet:
1. why "it seems reasonable to aim for approximately 70dB SNR in our ADC"? why not make the SNR larger than 74dB?
2.what's the meaning of "For 31 levels"?

Hi JoannesPaulus, I beg your help!! Help me again please, thanx you!!

 

[sethtalk]

Re: How to calualte the capacitor size when design pipeline

hi,wjxcom:
in your calculation for cap. size, it shoule be
4*kT/C = 77uV-rms^2, not kT/C = 77uV-rms^2, so the cap size is 2.8pF
your question
1. why 70db seems reasonable? i think the author means that in the power/area
consideration, the reasonable SNR is 70dB

could you send me the thesis ? i am interested about it!

wutehlun(at)gmail.com
darren wu

 

[wjxcom]

Re: How to calualte the capacitor size when design pipeline

Hi all: I'm sorry, I forgot to upload the thesis

this the thesis in the attachment!

and what's the meaning of "For 31 levels"?

 

[sethtalk]

see p32, The first stage has 31 quantization levels,
so you need 31 cap
in conventional MDAC architecture,
fully differential implies (2* KT/C) ,sampling phase/amplification phase implies (2 *KT/C),so total noise is 4KT/C ,
i don't understand why the thermal noise is only KT/C in this thesis

 

[wjxcom]

Hi sethtalk: do you know why "The first stage has 31 quantization levels"?

help me please, thanx!

 

[sethtalk]

because the first stage is a 5bit MDAC stage, so you need a 5 bit DAC inside the MDAC,