gyrajput
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hello all,
i tried to add packge and component in and function
my top code is :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : out STD_LOGIC);
end top;
architecture Structural of top is
component and_gate IS
PORT ( a, b: in std_logic;
c: out std_logic);
end component;
Signal temp1, temp2: std_logic;
begin
and1: and_gate
PORT MAP(a, b, temp1);
and2: and_gate
PORT MAP(a, c, temp2);
and3: and_gate
PORT MAP(temp1, temp2, d);
end Structural;
then i write a new vhdl module
entity and_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end and_gate;
architecture Structural of and_gate is
begin
c <= a AND b;
end Structural;
my check syntex is ok
but code is not synthesize
error is as followes:-
ERROR: The Top module has not been specified. This can happen if no sources have been added to the project,
please tell me how to call package and component in xilinx.....
i tried to add packge and component in and function
my top code is :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : out STD_LOGIC);
end top;
architecture Structural of top is
component and_gate IS
PORT ( a, b: in std_logic;
c: out std_logic);
end component;
Signal temp1, temp2: std_logic;
begin
and1: and_gate
PORT MAP(a, b, temp1);
and2: and_gate
PORT MAP(a, c, temp2);
and3: and_gate
PORT MAP(temp1, temp2, d);
end Structural;
then i write a new vhdl module
entity and_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end and_gate;
architecture Structural of and_gate is
begin
c <= a AND b;
end Structural;
my check syntex is ok
but code is not synthesize
error is as followes:-
ERROR: The Top module has not been specified. This can happen if no sources have been added to the project,
please tell me how to call package and component in xilinx.....