Hi,
I think C is the corect answer for efective setup time and hold time, max frequency is 166.7MHz.
Tsetupeff=TclkFFQ+(Txor-Tclkdelay)-Tsetup
Tholdeff=(Txor-Tclkdelay)
TP=TclkFFQ+(Txor-Tclkdelay)+Tholdeff
thanks,the ppt is very good ,could you upload others ppt?
another question:from the ppt ,I want to ask,we don't know the period of clk ,how to calculate the tsu and thold?
from the ppt,the page 26 I think
the tsueffective=txor+tsu-tclk=2+2-1=3
theffectiv=th+tclk-txor=2+1-2=1.
is it right?
As of hold time, we are talking about IN ->Q, the orginal Th=2ns, for path Q to Q, hold time is fine. but for path IN to Q, even though we have Tp_xor=2ns, but we still have 1ns clk skew, so, the new hold time for IN shoul be met: 1ns.
Folks,
I can't download the file 13[1].SeqCktTiming.ppt because I don't have enough points as a newbie.
Can someone please email it to me at
abzrh(at)hotmail(dot)com
Thanks!!
Added after 59 minutes:
Folks,
I can't download the file 13[1].SeqCktTiming.ppt because I don't have enough points as a newbie.
Can someone please email it to me at
abzrh(at)hotmail(dot)com
Can someone elaborate more on calculating the max clock frequency...
Even I think it should be 125Mhz...so for those who gave the answer as 166...can u plz explain how u got it?
i think the answers of these questions are C.
Tc=Tclk-q+Txor+Tsetup=4ns+2ns+2ns=8ns,so the f=125MHz.right?
hi,gck.
could you mail your ppt to me? I can't download it because my point isn't enough.
my email :jimaaa0@gmail.com