How to calculate the propagation delay of a circuit?

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Suppose the circuit below, where each logic gate has a propagation delay given by (tPLH + tPHL) / 2.





The correct method of calculating the circuit's propagation delay would be to add the gates that take the longest time to reach the output, which in this case would be:
I1 + A1 + O1 + O2 = 50.5 ns ?
 

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Hi,

basically correct.
You need to calculate each path:
A->X
B->X
C->X

but ... the circuit includes some issues.
The minor issue is: Why does the signal B cross two other signals. If yu re-order the signals (A-C-B) you omit the 2 crosspoints and the circuit gets much simpler to read.

Then the major issue becomes visible:
The bottom input of A1 as well as the top input of A2 is not driven. With this the input level is not determined .. and thus the output is not determined.
So the whole output X is not determined. So the whole circuit makes no sense.

Now one may guess that there is a junction point missing, that connects B with the inputs of A1 and A2. But I don´t think so, because then the signal B on it´s way to I3 crosses itself. No one would draw it this way.

Klaus
 
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I took this circuit as an example from Google just to check if the calculation method was correct. Thank you for clarifying my doubt and pointing out the problems in the circuit

D.A.(Tony)Stewart said:
Correct.
Click to expand...

Thanks
 

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TPLH and TPHL are often unequal and also vary gate-to-gate
and gate-w/-load by construction. The result of any such
figuring will not match any particular path through the
schematic.

The next step up the ladder would be to assign for each output
node, from the input conditions, the expected transition and
its direction-delay. If you knew them separately. You might find
the exercise interesting. Or not, depending on goals.
 

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