limitless_21
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HI All,
Here is a basic question based on synthesis. This is in regards with the cadence tool RC being used up for synthesis.
Earlier we were using WLMs (WireLoad Models) - by this we can calculate the interconnect resistance, capacitance and the area with the values given in the corresponding tables.
Currently now as for the new flow of Cadence i.e PLE flow, we are sourcing up the LEF and the Cap-table files. - With these files being sourced up , how can we calculate the interconnect resistance, capacitance and area of the net ?
And how different it is from wire load model - i mean performance wise how is the new PLE flow different from Wireload model flow.
Thanks
Tanvi
Here is a basic question based on synthesis. This is in regards with the cadence tool RC being used up for synthesis.
Earlier we were using WLMs (WireLoad Models) - by this we can calculate the interconnect resistance, capacitance and the area with the values given in the corresponding tables.
Currently now as for the new flow of Cadence i.e PLE flow, we are sourcing up the LEF and the Cap-table files. - With these files being sourced up , how can we calculate the interconnect resistance, capacitance and area of the net ?
And how different it is from wire load model - i mean performance wise how is the new PLE flow different from Wireload model flow.
Thanks
Tanvi