how to calculate the harmonic distortion?

[triquent]

For the envelope detector, load RL=10kohm
1) find a vlaue of C that can achieve suitable filtering for a 3kHz bandwidth baseband signal.
2)calculate the harmonic distortion for an input voltage of 5mV. Assuming the diode to be sufficently represented by the first three terms in the Taylor series expansion.

ps. AM detector circuit diagram(diode followed by a low pass filter)


-----diode------------
-------------|-----|
------------RL----C
-------------|-----|
----------------------

Added after 22 minutes:

My thoughts about the Q:
1) for low pass filter, ω0=1/RC, is the bandwidth 3kHz. so C=1/Rω0
2)for the envelope detector, the input signal is v(t)=v0(1+mcosωmt)cosω0t
ωm is the modulation frequency, ω0 is the rf carrier frequency(ω0>>ωm) and m is the modulation index(0<=m<=1). for the diode i(v)=Is[exp(vd/VT)-1], use Taloy expansion about V0, get i(v)=I0+vGd+v2/2*Gd'. The substitute v(t) in to the i(v), we get I(t)=.....v02Gd'/4(1+m2/2+2mcosωmt+m2/2*cos2ωmt+....)+....
in which, the cosωmt term is the harmonic term and cos2ωmt is the harmonic distortion. So harmonic distortion=(v02Gd'/4)*(m2/2).
v0=5mV, but we also need to know the m and I0 and Is(diode's quiescent bias point) to calculate harmonic distortion. These parameters the question didn;t give out. So Anything wrong with my calculation?

 

[flatulent]

Do not restrict the bandwidth so much. All you need to do is remove the carrier term. Next look at the circuit in the time domain. The rising modulation cycle will bump up the capacitor voltage. The falling edges will have no effect. Only the parallel resistor will bring the capacitor voltage down.