Haier
Junior Member level 2
DSP: TMS320C6713B
FPGA: Xilinx V7
interface: EMIF
Data Bus: 32-bit
Bus clock: 100MHz
Then how to calculate the effective bandwidth?
Could anyone tell me the method...
FPGA: Xilinx V7
interface: EMIF
Data Bus: 32-bit
Bus clock: 100MHz
Then how to calculate the effective bandwidth?
Could anyone tell me the method...