How to calculate the depth of FIFO and what are the designs contraints for it?

[Gireesh]

How to calculate the depth of FIFO and what are the designs contraints for desiging it?

 

[microe_victor]

cummings fifo

The depth of a FIFO depends on the data processing rate both on the send side and receive side.

The size of a FIFO should takes the "worst data transfer" into consideration.

Generally, the worst situation contains two transfers.

Then the data length of the two transfer should be equal to the sum of the FIFO depth and the data processed by the reciver at the very time spend on sending them.

holp it helps

 

[satyakumar]

interview question fifo depth

Hi,
Lot of material is available in google as well as in this board just try seraching

 

[orangelogic]

fifo diagram

hey microe_victor, can u expand a little more on the FIFO depth calculation.... thanks

 

[ankit12345]

worst case fifo size calculations

orangelogic

For what u need FIFO depth calculation????
Is is interview purpose????where diff questions with diff set of solutions can be found....
If ur calculation for ur project.....then most of the time microe_victor sol suits.......

what ur searching for????

 

[subramanyam]

fifo depth calculation cummings

One of the most common questions in interviews is how to calculate the depth of a FIFO. Fifo is used as buffering element or queueing element in the system, which is by common sense is required only when you slow at reading than the write operation. So size of the FIFO basically implies the amount of data required to buffer, which depends upon data rate at which data is written and the data rate at which data is read. Statistically, Data rate varies in the system majorily depending upon the load in the system. So to obtain safer FIFO size we need to consider the worst case scenario for the data transfer across the FIFO under consideration.



For worst case scenario, Difference between the data rate between write and read should be maximum. Hence, for write operation maximum data rate should be considered and for read operation minimum data rate should be considered.



So in the question itself, data rate of read operation is specified by the number of idle cycles and for write operation, maximum data rate should be considered with no idle cycle.



So for write operation, we need to know Data rate = Number of data * rate of clock. Writing side is the source and reading side becomes sink, data rate of reading side depends upon the writing side data rate and its own reading rate which is Frd/Idle_cycle_rd.



In order to know the data rate of write operation, we need to know Number of data in a Burst which we have assumed to be B.



So following up with the equation as explained below: Fifo size = Size to be buffered = B - B * Frd / (Fwr* Idle_cycle _rd ).



Here we have not considered the sychnronizing latency if Write and Read clocks are Asynchronous. Greater the Synchronizing latency, higher the FIFO size requirement to buffer more additional data written.



Example : FIFO Depth Calculation


Assume that we have to design a FIFO with following requirements and We want to calculate minumum FIFO depth,



A synchronized fifo
Writing clock 30MHz - F1
Reading clock 40MHz - F2
Writing Burst Size - B
Case 1 : There is 1 idle clock cycle for reading side - I
Case 2 : There is 10 idle clock cycle for reading side - I



FIFO depth calculation = B - B *F2/(F1*I)



If if we have alternate read cycles i.e between two read cycle there is IDLE cycle.

FIFO depth calculation = B - B * F2/(F1*2)



In our present problem FIFO depth = B - B *40/(30*2)

= B(1-2/3)

= B/3



That means if our Burst amount of data is 10 , FIFO

DEPTH = 10/3 = 3.333 = 4 (approximatly)



If B = 20 FIFO depth = 20/3 = 6.6 = 7

or 8 (clocks are asynchronous)



If B = 30 FIFO depth = 30/3 = 10

10+1 = 11 (clocks are asynchronous)



If 10 IDLE cycles betweeen two read cycles .

FIFO DEPTH = B - B *F2/(F1*10) .

= B(1-4/30)

= B * 26 /30

 

[vinod488]

fifo interview question

hi,
anyone can provide good material on FIFO,implementation details amd
Application point of view.

Thanks

 

[orangelogic]

fifo calaculation interview

this was very helpful

 

[go4sandesh_vsn]

interview question + fifo depth

thnx subramanyam....thts really a nice n very helpful info ....but

i think instead of

B - B * Frd / (Fwr* Idle_cycle _rd )

....

it shud be

B - B * Frd / (Fwr* (Idle_cycle _rd +1))

this is bcoz Read side data rate will be directly proportional to (trd + idle_cycle_rd*trd).........where trd is time period of read clock


plz correct me if i m wrong.........

 

[sunjimmy]

to calculate the depth of asynchronous fifo

Hi,

You can refer to the following FIFO diagram from Cypress datasheet. It provides a good overview of the architecture.

Added after 55 seconds:

 

[ls000rhb]

fifo + diagram

very clearly instruction!

 

[phoenixfeng]

depth of the fifo

sometimes designer aslo has to consider the load of CPU, if watermark of FIFO is reached , CPU must read it out . so if depth is just ok(meet the R/T rate), interrupt will happen within small interval

 

[deh_fuhrer]

synchronized fifo depth

can somebody please explain what does burst data means??

 

[go4sandesh_vsn]

depth of fifo

its simple...burst data means one or more data access at a time.....or in a better way u can take an example as: if u give command a memory controller to feed u with next FOUR data (in the next say four clock cycles) starting from some particular memory location ...then we say u r reading in a burst of FOUR....

hope u got tht

 

[vamsi_addagada]

interview questions on fifo

u go search in asic-world.com
is there in fifio depth
Fifo size = Size to be buffered = B - B * Frd / (Fwr* Idle_cycle _rd ).

 

[deh_fuhrer]

asynchronous fifo depth calculation

but what would we take while just designing a simple asynchronous fifo...(as the formula depends on burst length,B).I mean to say that can we assume this burst length value (either worst case or something like that).And what could be the worst case if we are exchanging ot transferring data between 300Mhz to 180Mhz???can anybody please give me the depth for this fifo...(please explain as I dont have any experience in fifo designing)....(Assuming that there is only one idle cylce between successive data read)...and what could be the depth of fifo when we are exchanging data between 180Mhz to 300Mhz for the same number of idle cycles......

 

[alam.tauqueer]

Depth of FIFO

good explanation by subramanyam.

 

[deh_fuhrer]

Re: Depth of FIFO

but I am still confused about the burst length...

 

[bharat_in]

Re: Depth of FIFO

@subramanyam
Can you please explain, how to derive depth, when there is no such thing as burst length?

 

[deh_fuhrer]

Re: Depth of FIFO

@subramanyam
Can you please explain, how to derive depth, when there is no such thing as burst length?

Hi Subramanyam,
I am also looking forward for your reply regarding this...As I still dont understand the concept of burst length...