There is a very easy way to calculate the effective gate capacitance, say for a FO4 chain. I could give a detailed description here, but it would be better for you to just go through the Circuit Simulation Chapter in CMOS VLSI Design: A Circuits and Systems Perspective by Weste and Harris. The basic idea is to make a FO4 inverter chain, and in one of the branches, replace the transistor with a dummy capacitor. HSPICE has an optimization routine which can change the capacitance value to match the fall/rise time of the inv-chain. Once the optimization converges, the dummy cap value will give you the equivalent gate capacitance of the inv-stage. The HSPICE script and explanation is given in the textbook. Also, I'd highly recommend this book for learning VLSI, it has relevant design examples and more useful explanations compared to Rabaey.