Re: biasing voltage
I sit in front of a circuit simulator (Cadence is the industry standard, PSPICE is not bad) to determine the biasing conditions, feature sizes, voltages and such. In the conventional circuit you provided, Vbn1 and the the sizing of the current sink transistors at the bottom (that's not a very good current sink though) would depend on what DC current you want. Same applies to the PMOS current source on top. The differential pair transistor sizings would depend on what kind of a transconductance gain you want -- larger the W/L ratio, larger the gm.