how to calculate slack in a digital circuit

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hi
can any one tell me how to calculate slack in a circuit consisting of 2 ff's. it is a synchronus circuit. the output of the first flip flop is given to some combinational ciruit which has some propogation delay. output of this circuit is fed the next ff. thus how to calculate slack in this ciruit and what is the equation for it. also what are the constraints on cycle time of the clock also which inturn will decide the max frequency of the circuit.

also can any one tell any book which covers these topics.

thanks
pritam
 

max(Tpd)<Tclk-Tstp-Tczq-Tskew
min(Tpd)>Thold-Tczq+Tskew
Tpd:the delay of the combinational logic between of two FF;
Tstp:the setup time of FF
Thold:the hold time of FF
Tclk: the period of clock
Tskew:the clock skew of clock
Tczqropagation delay of FF,time from arrival of clock signal till change at FF output.
 

You can search around "setup time" & "hold time" in the web. Also, many ASIC books,including synopsys Primetime manual contain this topic. If you want to make your chip function well, you have to know "setup & hold time"
 

if you are doing ASIC design, sure the synthesis tools and layout tools will list the worst slack path based on the constraints you feed into the tools.

if you are doing full customer, you have to run simulation to know how critical the path is regarding you expectation.

in the case you want to mannually calculate delay for some estimation cases, the book of Rabaey and Jacobs are very helpful

 

Where can i get synopsys prime time softwar manual on net other than synopsys website.
 

This is a nice app note from Motorola regarding SDRAM connection to a PowerPC.
It has a section about timing analysis.
**broken link removed**
Check also Altera and Xilinx about timing
 

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