how to calculate LUT usage in fpga design?

I also refered its schematic and technology map viewer. but it is showing the design using different no. of input LUT not 4 input LUTs.

Click to expand...

I assume, that Xilinx is also able to show the synthesized netlist, involving the LUT type available with the target FPGA. Altera Quartus is e.g. showing it.

i tried to find the netlist file but i didn't get it. i'm new to xilinx, there might be some settings to do to generate it.

I would also expect a convenient graphical representation of the netlist, but I'm not familar with Xilinx tools. You can export a netlist for gate level simulation, however.

In technology map viwer it is showing LUT level schematic.

vsheladiya said:

In technology map viwer it is showing LUT level schematic.

Click to expand...

That's what I expect. You previously stated, Xilinx technology map won't show the real LUT mapping. This sounds strange, but I'm not able to check it.

At that point of time i meant to say it is not showing LUT4 usage as it is showing into a report. it shows in form of 2, 3 or 4 input LUT for my design.

All luts are 4 input (or 5 or 6 depending on technology). If you use 2 inputs, then the other 2 are unused, and cannot be used by anything else.

So every lut is 4 inputs regardless of whether it says 2/3/4 on the map viewer. Its the same with altera and Xilinx.

Thanks again TrickyDicky...

If function with 5 input and 2 output is there and suppose architecture supports 4 input LUTs then how many LUT it will use?

FvM said:

That's what I expect. You previously stated, Xilinx technology map won't show the real LUT mapping. This sounds strange, but I'm not able to check it.

Click to expand...

Xilinx also has "FPGA_Editor", which is similar to Altera's Chip Editor. It shows the FPGA, locations of the various elements and switchboxes, routings, configuration of objects, etc...

All luts are 4 input (or 5 or 6 depending on technology). If you use 2 inputs, then the other 2 are unused, and cannot be used by anything else.

So every lut is 4 inputs regardless of whether it says 2/3/4 on the map viewer. Its the same with altera and Xilinx.

Click to expand...

that is somewhat misleading, as most FPGAs are only approximately like this in modern times. Xilinx uses "6LUTs", but these can be configured as dual 5 input LUTs if the inputs are the same. Further, Xilinx also has external logic functions. Obviously the carry chains, but also the "f7" and "f8" muxes which allow two 6LUTs to be used as a 7LUT, or 4 6LUTs to be used as an 8LUT. Altera also has similar features called adaptive LUTs.

If function with 5 input and 2 output is there and suppose architecture supports 4 input LUTs then how many LUT it will use?

Click to expand...

between one and four.

The specific function will determine the exact number. For example, the two-LUT case occurs when a 4LUT is used with the Chip-Enable (or reset/set) of a register to form the 5-input function. (as a side note, remember that the V5's 6LUT+register supported both set/reset independently, while S6/V6 have more registers but only support a single set/reset.)

Xilinx uses "6LUTs", but these can be configured as dual 5 input LUTs if the inputs are the same.

Click to expand...

This is only true for newer Xilinx devices, as far as I'm aware of. The original poster never mentioned the utilized FPGA family, but the statements about 4-input LUT suggest an older family, e.g. Spartan III.