How to calculate differential pair target Zdiff?

[Rimvis123]

hello everyone,

I do not understand how to calculate diff pairs with saturn or Sierra circuits programs. I need to route 100ohm (this line is from crystal oscillator to microcontroller so 100 ohm is right yes?) impedance diff pair line. I'm trying to calculate it, but I don't understand what dielectric height, ΔW and Trace Thickness (T) ( mm ) I need to put. In dielectric height I need put 1,6mm as my full pcb height or height between top and second layer?

 

[D.A.(Tony)Stewart]

You may not need a differential impedance or a coplanar waveguide or even a controlled impedance.
Is the path length < 1/20 wavelength?

e.g. if the XO was 350 MHz your max trace length is likely greater than your trace.

Even if your rise time was 1 ns = tR (or Sr in Saturn) usin 1/4 Sr for the spectral content of significant harmonics is slower than the propagation delay of 35 mm , so does this make sense? It means the echos are faster than the risetime for a few mm trace length, so any short single trace will work fine from an active XO (Crystal Oscillator)

 

[Rimvis123]

My path lenght (if I understand that correctly) is shown in picture below. And my crystal oscillator is 32MHz. So in this case my max trace lenght is more than enough, yes?

 

[barry]

My path lenght (if I understand that correctly) is shown in picture below. And my crystal oscillator is 32MHz. So in this case my max trace lenght is more than enough, yes?

View attachment 188660

Why don’t you flip the oscillator around to shorten the path?

But to answer your original questions, just look at the diagram YOU posted. Dielectric height is the height between the trace and plane. Trace thickness is, um, the thickness of the trace.

 

[D.A.(Tony)Stewart]

Show link to XO. uC use single ended input and driver output not differential input

 

[Rimvis123]

Why don’t you flip the oscillator around to shorten the path?

But to answer your original questions, just look at the diagram YOU posted. Dielectric height is the height between the trace and plane. Trace thickness is, um, the thickness of the trace.

1. It need to be in this possision. It's not my own pcb, I just need to calculate things that I asked in this post, so original owner said, that this need to be like this.
2.Dielectric height - is 0,2104mm?
3.So that i choose 0.07 is good?

 

[D.A.(Tony)Stewart]

Show links to U4 and X1 datasheets

 

[Rimvis123]

U4 - https://www.mouser.lt/datasheet/2/389/dm00344191-1798909.pdf
XO - https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-306&lang=en
and onother one which i use - https://www.mouser.lt/datasheet/2/905/ndk_08142018_NX2016SA-32M-EXS00A-CS06465_SS-1389053.pdf

 

[D.A.(Tony)Stewart]

This is what we call an XY question. TS assumes the problem which is not the problem.

You assumed controlled impedance was the problem and is an XO = active crystal oscillator. But it is neither true for this.
It is just a passive crystal, X not an active device but passive with load C's C35 and Cxx hidden.

Worse yet, the 1st X he chose , uses 2 pins in a non-std adjacent pads
Seiko Epson

While most X SMDs are diagonal corners with opposite diagonal corners connected to Gnd such as your alternate NDK P/N which will fail.

ECS, NDK, Kyocera, NDK etc

This means you will have a hard time finding an alternate source from Seiko's non-std pads.

So what is your real problem? To me it looks like a design problem with no second source using a unique pad layout from Seiko..

 

[Rimvis123]

So i should not use both C's with this XO? And overall I need to use different XO? Sorry for questions, but it's first my and my friend bigger project.

 

[D.A.(Tony)Stewart]

You can only use the Seiko X part in this design, which locks you into one source.

The diagonal corner pins for a shorter Crystal is more the "defacto std." with many sources.

It also means for this problem Controlled impedances is irrelevant on diff traces but the value of C is critical for accuracy. 12.5 pF std load means the two caps equivalent series Ceq is 12.5 so 1/25 pF + 1/25 pf = 1/12.5 pF

 

[Rimvis123]

But why I need "Seiko"? I just used XO from stm32 datasheet. And overall if that is a problem, can I use OX like in this project?https://andybrown.me.uk/2021/10/10/stm32wb55/

 

[D.A.(Tony)Stewart]

You said here it is a 32 MHZ oscillator yet your 1st link it points to a tuning fork 32 kHz Crystal

Now it starts to make sense.

Don't worry we all make rookie misteaks. XO is active . This design is passive X , the active part is in the uC.

32.768k Crystals have a different defacto layout than MHz Quartz crystals
So there are alternate sources

These crystals use different pads and different pF load, so do not substitute unless you can live with 1 second timing clock error due to wrong C load caps.

The 32 MHz uses pin 1,3 with 2,4 grounded
the 32.768 kHz uses pin 1,2 with 3,4 floating. but if you read the datasheet, some use different pin numbers like 1,4 for tuning fork 32.768 kHz so pay attention to details. There is no design reason why this 32 kHz xtal could not have been flipped around and that is the reason why it is at one end to be close to the caps and uC and eliminate parasitic traces which add 3 pF/cm like in his design. That part you can verify in Saturn using no ground plane. or large gap . Also he should never run signal traces under crystal signals on top for this causes crosstalk and affects SNR of clock. Maybe ok, may not.

if you want an accurate clock for timing errors in < 10 ppm , he should have chosen an XO rather than a passive X + 2 caps. XO's are designed to be more accurate. e.g. https://www.mouser.lt/datasheet/2/137/TG_3541CE_en-1601070.pdf 1.9 ppm 0 to 50'C TCXO here

That is my final recommendation on this XY question. But if ppm error not an issue, what you have may work. Just don't mix X with XO and kHz and MHz.