how to build integrated clock gating cell ?

[honeyxyb]

integrated clock gating cell

Hi, all:
I am trying to optimize power of my chip , and I am using clock gating
methedology , because my library has no integrated clock gating cell , so I
use multi-cell to build a clock gating cell ( OR, LATCH AND INV etc) , but I found
it's difficult to meet timing of clock gating check , and I have requied Astro place
them together.
So I want to build a integrated clock gating cell to improve the effect. But I don't know how to do it, I have browsed all the documents of STAR-MTB(Synopsys) , but no detail informations about how to generate it, can anybody help me?

Thanks!

 

[tarkyss]

clock gating cell

if you have star_mtb, i remeber there are two demo, one is dff, another is or(i dont remeber exactly), you can follow the demos

 

[honeyxyb]

what is integrated clock gating?

hi, I can use star-mtb generate all the other standcell (including DFF ,Latch, AND , INV ,BUF , OR ,ADD, etc..) except integrated gating cell, but when I generate clock gating cell , the tools can't work , it report " can't initialze output port ...."

 

[tarkyss]

integrated clock gate cell

sorry, i have not used star_mtb for three years, the error generated when you run sml?
the port type is configured correctly in grd file?

 

[sam31]

integrated clock gate

You need a dedicated cell for gating clock in your design lib
These cells are designed for this task

 

[honeyxyb]

Hi all:
Are there more perples familier with this?

 

[atulaxc]

Some nice **broken link removed**