Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to build a VCO behavioral model?

Status
Not open for further replies.

marylin

Newbie level 4
Newbie level 4
Joined
Oct 11, 2007
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,309
vco design

I was asked to build a vco behavioral model(0.13um CMOS),how do it?

should I design a VCO from the transistor-level or system-level(bottom-up or up-bottom)? how to do it? And what the process of build a behavioral model is ?

thanks!
 

vco design

you can do it using verilog-A.
and you can also do it with ads or matlab.
 

    marylin

    Points: 2
    Helpful Answer Positive Rating
vco design

Constructing a VCO in Verilog A would mean that you are making a linear model of the VCO. This can be implemented using a simple transfer function like wout =Kv/s*Vcontrol. So, you also need to model amplitude limiting, which is very important for phase noise to dominate. Also, you need to model the power supply sensitivity which also puts a ripple of the power supply into the output waveform.

There are a lot of non-idealities you have to model as well. Starting point would need you to get the required gain, Kv. You also can model the non-linearity in the gain as well.
 

    marylin

    Points: 2
    Helpful Answer Positive Rating
Re: vco design

Vamsi Mocherla said:
Constructing a VCO in Verilog A would mean that you are making a linear model of the VCO. This can be implemented using a simple transfer function like wout =Kv/s*Vcontrol. So, you also need to model amplitude limiting, which is very important for phase noise to dominate. Also, you need to model the power supply sensitivity which also puts a ripple of the power supply into the output waveform.

There are a lot of non-idealities you have to model as well. Starting point would need you to get the required gain, Kv. You also can model the non-linearity in the gain as well.


but how can I build the vco model,shoul I copy the mathematical from the book or I can do it myself?
 

Re: vco design

marylin said:
I was asked to build a vco behavioral model(0.13um CMOS),how do it?

should I design a VCO from the transistor-level or system-level(bottom-up or up-bottom)? how to do it? And what the process of build a behavioral model is ?

thanks!


If you use spice simulation, you can use Verilog-A, commonlib of eldo has the vco behavior model.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top