danesh
Full Member level 3
hi,
Im designing a circuit using mgsf1n02lt1 n- mosfet. The vdd would be 13.8V. Can any one suggest how do i bias the gate inorder to get 6V at the drain(output) instead of 0 volt ? Thanks for your concern
Im designing a circuit using mgsf1n02lt1 n- mosfet. The vdd would be 13.8V. Can any one suggest how do i bias the gate inorder to get 6V at the drain(output) instead of 0 volt ? Thanks for your concern