how to begin a PLL design..

I will begin a PLL design as my thesis for master degree in China. Here are my aim and puzzles,and I hope you can give me any suggestion.Thank you very much!
AIM:a low phase noise PLL
PUZZLES:
(1)Which frequency is the suitable? I always find many papers on IEEE about PLLs which have a 2.4G frequency.Besides this frequency,which frequency is useful in the industry area? 900M,1G or the others?
(2)In order to reduce the phase noise in PLL,which architecture is suitable or which papers I can refer to in the recent years.
/Thank u.

look at this website for some INFO: rfshop.com.au

i think to do a good thesis try to select a frequency have new use like 5 GHz , used in wireless networks

the PLL is a system so u must know , how to analyze this system and the models for this system

after system anlysis , u go to circuit level design
try
www.circuitsage.com
www.rfcafe.com
and national web site there r many app notes
and also motorola web site

trashbox said:

PUZZLES:
(1)Which frequency is the suitable? I always find many papers on IEEE about PLLs which have a 2.4G frequency.Besides this frequency,which frequency is useful in the industry area? 900M,1G or the others?
(2)In order to reduce the phase noise in PLL,which architecture is suitable or which papers I can refer to in the recent years.
/Thank u.

Click to expand...

Firstly, you should decide which domain your PLL will be used. If it will be used for wireless communication as a frequency synthesizer, then the frequency is generally above 1G. However, if it is for clock generator in MCU or CPU, then the lower frequency, about 100MHz, is well. In addition, it can also be used in clock and data recovery circuit. To sum up, you should consider your requirement & application at first.
About lower phase noise in PLL, the PFD & Charge Pump, Divider have more mature architecture for a general PLL compared with VCO. At the same time, the phase noise generated by VCO dominates the whole PLL. So if you more focus on the lower phase noise characteristic & the PLL is used in communication environment( that is to say, need a higher frequency), then the LC VCO is more suitable.
If any wrong occurs Please correct!

Thank all.

In the last days,I have read some papers and find that designing PLL need much theory such as feedback theory,signal&system.And then is the circuit level. I will share my feelings with you during studying PLL at this forum in the coming days.

Hope you a nice day!

Hello,I am a starter in EDA.Recently,I am busy in doing my graduate design,and there are so many trubles.One of them is how to use pll block in a FPGA,how to spacify its parameters for altclklock?
Hoping help!Thanks!

I think this file might help u.

“Submicron CMOS Components for PLL-based
Frequency Synthesis” by Syed Irfan Ahmed, B. Eng.,

This thesis presents the design, the design methodology and the submicron implementation of a PLL-based integer-N frequency synthesizer with an external loop-filter. The synthesizer is implemented in 0.25 µm, TSMC, digital CMOS process. The frequency range is from 10 MHz to 300 MHz

It is not easy to design a good PLL ( low phase noise).