How to avoid using clk buffer ?

[efundas]

How to avoid clk buffer

I am synthezing my design for Xilinx device. I find that one of my input signal which is not a clock is being through the global clk buffer. How can I force the synthesis tool to not use the clk buffer for this input.

 

[cfft]

Re: How to avoid clk buffer

If you use synplifypro,you can find it from its help menu.
I forget it now.It may be add the attribute ,'syn_no_clkbuf',to the input clk.
You can try it or find from the help menu through finding syn_no_clkbuf.
Good luck!

 

[zape]

If you want to avoid the use of a global clock buffer, you may "prohibit" it by means of a constraint in the ".ucf". Check with Xilinx documentation but it is sthg like: CONFIG PROHIBIT = GCLKBUF0;

 

[efundas]

But that constraint will disable the use of the BUFG0.
My problem is that for a particular I do not want to use the clock routing. If I disable the use of BUFG0, it will take some other buffer.

 

[zape]

Then if what you need is that BUFG0 to be used for an special line of yout design you will have to instantiate the bufg in your design.

 

[samuel_john]

Re: How to avoid clk buffer

hi

The maaping of non-clock signal into bufg occurs depending on the load on the signal. If the load on the signal is high or if the bufg is free then the unwanted signal may get mapped into bufg,

either u should resctrict the usage of bufg by going to synthesis xilinx specific option.u can select the number of bufg to be used in ur design and instiated that bufg with the respective clock signal so that the high fanout signal will not map into bufg...

but i would like to known why u don't want to use bufg, so that i can provide u more help if required..