How to avoid unwanted logic removal during synthesis?

permute said:

I'm more of an FPGA guy, but some optimizations -- retiming in particular -- modify the design in logically safe ways in order to meet timing. The nets may still be in the design under a different name.

Secondly, are you certain you are building/testing the correct files? "randomly removing used logic" often occurs when there are accidental duplicates of modules/files/netlists where the simulation is done with a different set than the synthesis/implementation.

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KHDAK said:

Hi All,

I am synthesizing a processor design with Cadence RTL compiler. The synthesized netlist works fine (in simulation) and contains all necessary logic when I set a loose clock constraint (5000ps). But when I synthesized the same files with a tighter clock constraint (1800- 3000ps) the RTL compiler meets the timing constraint but randomly removes some of the registers(i.e Register file of the processor) in the synthesized netlist, which are required for proper operation of the design and are not some undriven or extra logic. Is there a way to instruct RTL compiler what not to remove?

The attributes I am using are as follows:

set_attribute hdl_track_filename_row_col true /

set_attribute hdl_undriven_signal_value 0

set_attribute hdl_infer_unresolved_from_logic_abstract false /

set_attribute information_level 2



Thanks.

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englishdogg said:

I would check the logfile to identify the reason for which the register is removed. TRy setting the information level to 9 and search that register. RC will tell you a reason why the registers where optimized.

Retaining hierachies you mean avoid ungrouping. I would say yes, set the attr auto_ungroup to none.

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