How to avoid shoot through in FET push/pull stage?

Hi - I've always wondered about this... If you have a chip with a FET push/pull output, how do you avoid shoot through between the two FETs? I mean - assuming you have an N-FET on the bottom, and a P-FET on the top, and their gates are connected - at some point when switching from high to low or from low to high, both FETs will be on.

I'm thinking that their gates must not be connected, and their is some sort of circuitry in front of them to make sure shoot through doesn't happen. What do these circuits look like?

Thanks!

I assume that your application is a CMOS output driver.

These application have two main specs:

1. Current rise time

Today the drivers are faster than what could be tolerated by the passive parasitics like bondwires. So to reduce the amount of transient voltage drop over supply inductors the current rise/fall time should be strictly designed.

2. Charge Efficiency

That belongs a little bit to your short current issue. The driver is designed to bring this current at the time of output change to zero. So there is no charcge loss, all charge for the load is delivered.


The first solution is done today by delay chains which drive individual segments of the output driver. So the segements are switched on in a time sequence. But there are switched off all at the same time. That is possible because if the output level settles there is no further static current which could make a high di/dt.

The second solution is to apply driver signal individual to the P and N. The driver is designed to have a small time where both driver signals are inactive. So high for P and low for the N. I could not figure out the detail but it is a crosscoupled NAND-pair where the feedback signals are delayed.

There is also simple "ballistic" timing skew, which can enforce
some break-before-make. Simply making the last few stages
of the predriver chain asymmetric, favoring turnoff over turnon,
can get you most of what you want. However this is going to be
an "open loop" thing and process variation has to be accommodated
by excess break-time in the normal case.

Putting the cross-coupled logic in there, you'd have to put it a
fair way back in the chain and this also incurs a largish break time
if you're talking about big taper chains, like a 1A sync buck
output switch. That, or it's a huge and inefficient NAND
gate.

You can add a small delay such as 3-5nS to make sure Pmos on after Nmos off 3-5nS (should not connect their gates together in this case)