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How to avoid extra region lines after using regrid__silvaco to simulate FETs

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Risewisun

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Extra region lines after regrid__silvaco

Hello, everyone!
I'm learning to use silvaco to simulate FETs. But while I use regrid to make a fine design of the structure, there is always extra region lines in it. Please see the picture. How could I avoid these lines? remesh4-8minc.png
 

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