[SOLVED] how to avoid cascading of block ram

module ram
   #(parameter DW   = 29, // Data Width
    parameter AW    = 16,   // Address Width
    parameter DEPTH = 65536  
   )
   (input  clka,
    input  clkb,
    input  wea,
    input  [AW-1:0] addra,
    input  [AW-1:0] addrb,
    input  [DW-1:0] dia,
    output [DW-1:0] doa,
    output [DW-1:0] dob
   );

reg [DW-1:0] RAM [0:DEPTH-1];
reg [AW-1:0]    read_addra;
reg [AW-1:0]    read_addrb;

initial 
begin
RAM[0] = 29'b0;
RAM[1] = 29'b00000000000000000000000000000;
RAM[2] = 29'b00000101100010111001000010111;
RAM[3] = 29'b00001000110010011111010100111;
RAM[4] = 29'b00001011000101110010000101111;
RAM[5] = 29'b00001100111000000010000011111;
//.
//.
//.
//.
//.
RAM[65531] = 29'b01011000101110001110001111111;
RAM[65532] = 29'b01011000101110001110101111111;
RAM[65533] = 29'b01011000101110001111001111111;
RAM[65534] = 29'b01011000101110001111101111111;
RAM[65535] = 29'b01011000101110010000001111111;


end
always @(posedge clka)
begin
  if (wea == 1'b1)
  begin
    RAM[addra] <= dia;
  end
  read_addra <= addra;
end

always @(posedge clkb)
begin
  read_addrb <= addrb;
end


assign doa = RAM[read_addra];
assign dob = RAM[read_addrb];

endmodule