[SOLVED] how to avoid cascading of block ram

[seeker_123]

Hi everyone
I am using block ram in one of my design based on lookup table to store values.
But in 3 cases it is cascading two block rams. Because of this component delays is getting more than what I have given as constraint.
I am not getting why it is cascading. Is there any method with which we can avoid it ?
Please guide.

Thanks

 

[TrickyDicky]

I dont understand what you mean by cascading? BRAMs are synchronous so should not produce poor timing performance if they are chained as they have registers on all inputs and outputs.

Please post some example code that creates this "cascade"

 

[seeker_123]

Thanks for reply

I am also facing this problem first time.
I have written block ram code as mentioned in virtex user guide
but i have stored look up table values in initial block
Here I am attaching bram code.
Also I have attached .doc in which I have mentioned path which is violating from timing report and device view for same path.

module ram
   #(parameter DW   = 29, // Data Width
    parameter AW    = 16,   // Address Width
    parameter DEPTH = 65536  
   )
   (input  clka,
    input  clkb,
    input  wea,
    input  [AW-1:0] addra,
    input  [AW-1:0] addrb,
    input  [DW-1:0] dia,
    output [DW-1:0] doa,
    output [DW-1:0] dob
   );

reg [DW-1:0] RAM [0:DEPTH-1];
reg [AW-1:0]    read_addra;
reg [AW-1:0]    read_addrb;

initial 
begin
RAM[0] = 29'b0;
RAM[1] = 29'b00000000000000000000000000000;
RAM[2] = 29'b00000101100010111001000010111;
RAM[3] = 29'b00001000110010011111010100111;
RAM[4] = 29'b00001011000101110010000101111;
RAM[5] = 29'b00001100111000000010000011111;
//.
//.
//.
//.
//.
RAM[65531] = 29'b01011000101110001110001111111;
RAM[65532] = 29'b01011000101110001110101111111;
RAM[65533] = 29'b01011000101110001111001111111;
RAM[65534] = 29'b01011000101110001111101111111;
RAM[65535] = 29'b01011000101110010000001111111;


end
always @(posedge clka)
begin
  if (wea == 1'b1)
  begin
    RAM[addra] <= dia;
  end
  read_addra <= addra;
end

always @(posedge clkb)
begin
  read_addrb <= addrb;
end


assign doa = RAM[read_addra];
assign dob = RAM[read_addrb];

endmodule

thanks

 

[seeker_123]

hi everyone
can any one help me further in this ? I am stuck here.
Thanks

 

[TrickyDicky]

I think with such a large ram, multiple rams are innevitable.
Making Doa and Dob clocked?

 

[seeker_123]

Thanks alot TrickyDicky

Making Doa and Dob clocked?

by making doa and dob clocked it solved my problem. Though I didn't get why it was so......?

 

[TrickyDicky]

adding pipeline registers usually helps timing

 

[seeker_123]

Thanks for reply

adding pipeline registers usually helps timing

Yes but now it is not cascading any of ram too

Thanks again

 

[ads-ee]

There shouldn't have been any cascading of the RAMs there might have been additional multiplexing of the output of the RAMs that was occurring to get the depth you required.