rficlover
Newbie level 5
i wonder whether in the Cadence IC design software, there is any tool to automatically extract the parameters of interconnection, say, the parasitics of lines connecting the transistors.
Someone told me that I have to measure the line width and length myself, and calculate its parasitic res, ind and cap by some formula, and add the parasitics to the schematic.
The extraction tool in Cadence does not extract the parasitics of interconnection.
I guess someone might have some script for the Cadence to do that automatically.
Someone told me that I have to measure the line width and length myself, and calculate its parasitic res, ind and cap by some formula, and add the parasitics to the schematic.
The extraction tool in Cadence does not extract the parasitics of interconnection.
I guess someone might have some script for the Cadence to do that automatically.