How to apply b to a after a time delay: a<=#10b in Verilo

[flushrat]

About verilog-A question

In verilog, we can use apply b to a after a time delay: a <= #10 b
But in verilog-A, how can realize it?
Here is the verilog-A code:
integer a;
integer b;
@(V(clk),1) begin
a = b;
end

Simulation shows there should be some delay when applying a to b.
Now my method is apply b to a electrical first, then apply the electrical to a.
But it is quite complicated.

integer a;
integer b;
electrical c;
parameter td=1n;
c <+ transition ( b, td, tr, tf);
@(V(clk),1) begin
a = V(c);
end

 

[cooldog]

Re: About verilog-A question

How about this?

@(timer(td)) begin
a = tmp;
tmp = b;
end

 

[flushrat]

Re: About verilog-A question

Thank for your answer.
I am designing a series of DFFs, which are clock trigged.
But @timer cant be included in @(clk) statement.

How about this?

@(timer(td)) begin
a = tmp;
tmp = b;
end