How to append to an existing logfile without overwriting it for multiple Xilinx Vivado xvhdl and QuestaSim vcom compile commands

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Hi, I would like to compile multiple vhdl files separately but use the same log file for all without overwriting the content of the file (basically append to the file). How do I append to that one logfile in successive compiles? I would like to do that for xvhdl command in Vivado and also vcom command in QuestaSim.
 

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I also use Questasim but I have one DO file where all my files are listed in the order necessary for successful compilation.

I never used it but it might be possible to compile separate list1.txt list2.txt files inside the DO file, where list1.txt and list2.txt will contain the various VHDL files. Is this what you are trying to achieve?
But again I am pretty much sure that list1.txt should contain the VHDL files that must be compiled before the files inside the list2.txt. In the end the DO script will just flatten everything out and come up with the final compilation result.
P.S. said:
How do I append to that one logfile in successive compiles?
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Inside your simulation dir there is file created called "transcript", that is basically your compilation log!
 
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If it's an inlined output file direct like

>./myLogFile

Then >> appends instead of replaces.

If it's baked into the run files (?) then you'd fix it where you find it declared.
 

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