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Full Member level 5
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Hi, all: the file in the attachment is a OPA and this circuit puzzles me.
1.why we must use the Q6 and Q7 which act as a class B push-pull output stage? and why Q6 and Q7 can act as a class B push-pull output stage?
2.the dc biasing is designed so that Q8 and Q9 have equal-value small gate-to-source dc bias. This maximizes the linear Vout range. I do not know why.
1.why we must use the Q6 and Q7 which act as a class B push-pull output stage? and why Q6 and Q7 can act as a class B push-pull output stage?
2.the dc biasing is designed so that Q8 and Q9 have equal-value small gate-to-source dc bias. This maximizes the linear Vout range. I do not know why.