How to analyse Power consumption in ASIC?

[snaityma]

Re: ASIC Power analysis tools & methodology info is need

Hi all,

Please help How to analyse Power consumption in ASIC (i understand that their are several power analysis levels) & power design methodology.

Thanks,
Hawk.

Synopsys PowerMill will help you (in transistor level)
But if your design gate-count is very large,
it will takes a very long long time.
Reagrds,

 

[hawk]

what about other levels of power estimation?

 

[nanako]

sequencedesign's powerthreater can do it at rtl level so as synopsys power compiler

 

[snaityma]

Re: ASIC Power analysis tools & methodology info is need

Hi all,

Please help How to analyse Power consumption in ASIC (i understand that their are several power analysis levels) & power design methodology.

Thanks,
Hawk.

In RTL level, the cell libray must provide power information,
then, you can estimate power consumption,
but the accuracy maybe not good.
After you finish layout, you can get more accuracy value.

 

[jmichael]

RTL level Power Estimation - PowerTheater ( WattWatcher)
RTL level Power Reduction - PowerTheater ( WattSmith)
Gate level Power Estimation - PowerTheater (WattWatcher)
Gate level Power Optimization - Power Compiler
TR level power Estimation - PowerMill

 

[moorhuhn]

HSIM from NASSDA is a good, unfortunately pretty expensive tool.
You may simulate 40-60M transistors, it supports DSPF and the digital vectors from your gate simulation may be used as well. It is pretty fast
especially when you simulate memories. OK you have to play with
.params and you need a large memory for large circuits, but it is an
ultimate solution if you want to get also leakage in DSM.
Powermill and Pathmill are obsoleted.
Cheap gate level estimation may be done as follows. If you know the capacitance for each internal node, if you sample the toggle statistic
(e.g. no problem with Modelsim), you just need to calculate the power
dissipation on those capacitances and summ them together. If you want
to be more precise, you can have to precalculate an equivalent capacitance for each input of each SC in your library and add it to the above mentioned node capacitances. I was suprized about a good correlation of this method.
Nowdays there are 3D table chracterized libraries, expensive tools
but the precission ratio improvement is not so good as one may expect.

 

[kinysh]

what about designpower of synopsys.
is it popular for power analyse?

:roll:

 

[farmerwang]

the result relies on your test pattern

No matter what tool u use, the result depends a lot on the test patterns you used. You must design a pattern that can accurately reflect the typical working status of your device, you can also run a lot of patterns and caculate the average, but this is very time consuming.