How to analyse domino logic basic gates using multi threshold technique in pspice?

[dineshvv]

I choosed a ieee paper to do my final year project whose title is Effectiveness of Low power technique of dynamic logic under temperature and process variations.. Am having pspice version 9.2 software.. is it possible to perform power analysis to determine leakage power and delay in pspice.. Can anyone help me to do this project. I know the concepts but dont have idea in using software.. pls help me<<<>> If anyone interested reply me.. ill give my project details and modifications.. pls respond me asap.

 

[haykp]

pspice is mainly for pcb designs, so if you are doing pcb design then pcb is ok. But if you are doing chip level design, then I am not sure that pspice can solve such issues. I would suggest you to use hspice,hsim or spectre.

Please let me know the IEEE article name that you are referring to.

 

[dineshvv]

Hi haykp,,
Thank u for ur response.. ill attach my ieee base paper wit this msg.. Go thro it.. give me any idea abt dat.. In this paper they gave the simulation results for the several domino ckts using hspice.. They used dual threshold voltage technique. The main aim of my project is to find out leakage power and delay,, also to minimize it..

 

[dineshvv]

send me ur gmail id.. so that i can discuss with u in chat.. thanks once again for ur response.

 

[shandabogo]

iam doing the same !my mail shandabogo@hotmail.com