it is difficult to read the netlist, i am assuming that we are talking about the current sink for the differential pair. The following explanation is based on my assumption:
Your NMOS sink is in linear region.
Tou would need to increase the vds across it, which can only be incresed by incresing the gate voltage on the input of the differential pair.
If you cannot do that, thensee if you can redues the vdsat for the current sink.
If that is not possible, change the architecture.