DIGGING UP THE OLD THREAD....
Hi dharag,
were you able to find a solution to the problem?
Actually I am facing a similar problem now, while integrating a VHDL Xilinx IP in a Verilog top-level design and compiling with VCS.
I have created a separate filelist and compiling whatever us under unisims ans unimacro.
# VHDL unisim and unimacro
vhdlan -full64 -f $HW_TOP/sim/scripts/filelist_vhdl_lib.txt
(I am compiling everything under /primitive)
dpaul@crest:/home/shared/Xilinx/14.4/ISE_DS/ISE/vhdl/src/unisims$ ls
primitive secureip unisim_VCOMP.vhd unisim_VPKG.vhd
dpaul@crest:/home/shared/Xilinx/14.4/ISE_DS/ISE/vhdl/src/unimacro$ ls
ADDMACC_MACRO.vhd COUNTER_LOAD_MACRO.vhd MACC_MACRO.vhd
ADDSUB_MACRO.vhd COUNTER_TC_MACRO.vhd MULT_MACRO.vhd
BRAM_SDP_MACRO.vhd EQ_COMPARE_MACRO.vhd unimacro_VCOMP.vhd
BRAM_SINGLE_MACRO.vhd FIFO_DUALCLOCK_MACRO.vhd
BRAM_TDP_MACRO.vhd FIFO_SYNC_MACRO.vhd
But still I have the following errors (AFIFO36_INTERNAL.vhd is the first file under /unisims/primitive):
Code:
Parsing design file '/home/shared/Xilinx/14.4/ISE_DS/ISE/vhdl/src/unisims/primitive/AFIFO36_INTERNAL.vhd'
Error-[XSYMTABNOLIBMAP] Missing library map
Library logical name 'UNISIM' is not mapped to a host directory.
The show_setup command shows all of the mappings for the libraries. Please
use this command to validate that the named library above is mapped to a
physical directory in your synopsys_sim.setup file.
Error-[OVNOSELECT1_LIB] Undefined identifier
/home/shared/Xilinx/14.4/ISE_DS/ISE/vhdl/src/unisims/primitive/AFIFO36_INTERNAL.vhd, 46
AFIFO36_INTERNAL
use unisim.vpkg.all;
^
The symbol named 'VPKG' cannot be found in library 'UNISIM'.
Error-[OVNOSELECT1_LIB] Undefined identifier
/home/shared/Xilinx/14.4/ISE_DS/ISE/vhdl/src/unisims/primitive/AFIFO36_INTERNAL.vhd, 47
AFIFO36_INTERNAL
use unisim.vcomponents.all;
^
The symbol named 'VCOMPONENTS' cannot be found in library 'UNISIM'.
Error-[IEEEVHDLNOENT] Missing compiled design unit
/home/shared/Xilinx/14.4/ISE_DS/ISE/vhdl/src/unisims/primitive/AFIFO36_INTERNAL.vhd, 94
analysis-Parsing, "AFIFO36_INTERNAL"
architecture AFIFO36_INTERNAL_V of AFIFO36_INTERNAL is
^
The compiled design unit for entity 'AFIFO36_INTERNAL' is not found in WORK
library.
Please verify that the entity was analyzed successfully.
"/home/shared/Xilinx/14.4/ISE_DS/ISE/vhdl/src/unisims/primitive/AFIFO36_INTERNAL.vhd": errors: 4; warnings: 0.
.
.
.
MORE UNISIM based errors!
Can anyone please tell me what VHDL libraries should I be compiling in order to use the Xilinx VHDL IP (AXI_IIC_v1.02a)?
Right now I am trying to compile VHDL libs under WORK. Is this the correct approach (I doubt it)? In that case, should the Xilinx VHDL libs be compiled in a separate dir and then it needs to be mapped somehow?