dharag
Newbie level 5
Hello,
I am new to VCS, I am using VHDL DUT and system verilog environment for verification. my vhdl code uses unisim and unimacro libraries so how to include those libraries in vcs and simulate ?
Also what are the steps or commands to use this VHDL libraries in VCS ?
I am new to VCS, I am using VHDL DUT and system verilog environment for verification. my vhdl code uses unisim and unimacro libraries so how to include those libraries in vcs and simulate ?
Also what are the steps or commands to use this VHDL libraries in VCS ?
