How to add pad in DC automaticly?

[seasonyangd]

set_port_is_pad

Does anyone can tell me how to add pad located in the pad libraries automaticly when synthesis with synopsys DC?

 

[jeck]

synopsys dc set_pad_type

There is a insert_pad command in the synopsys. You can use it to insert pad. But it is not recommended by synopsys, you had better insert it by yourself--writting a file including your core, pad cell.

 

[Nobody]

dc set_port_is_pad

I try it in the pass time.
It's the must-be way to do in FPGA synthesis by DC.
Therefore I found most of the information reguard in insert_pad all
from Xilinx ftp/web. U can find it in their web.
BTW, I found many limit in doing auto insert pad .
U should follow this guid-line.
1. Name ur pad module interface signals in this rule
signal to/from pad begin with one prefix , for ex. pxxx and
avoid others signals from/to core begin with the prefix in the same
character.
Then u can do the set_port_is_pad with the wildscard world p* .
2. U should check ur pad library first. U must follow its cell function and
pin polarity. for Ex. high or low active enable sensity. Otherwise DC
will translate by add one invert buffer or complaint the no suitable cell to map.
3. after insert_pad , try compile it. If u look the netlist that have the Gtech
component.

 

[seasonyangd]

set_pad_type

Thanks for you reply. Yes, my library need tobe config to meet the functions but I dont know how to do it. Can you tell me???

 

[Nobody]

SPECIAL_PAD = GPDB35V
INPUT_PAD = PDIZ
INPUT_SCHM_PAD = PDISZ
PULLH_PAD = PDU04TZ
OUTPUT_PAD = PDT08TZ
INOUT_PAD = PDB08TZ

current_design = "pad"
set_port_is_pad {P0_7, P0_6, P0_5, P0_4, P0_3, P0_2, P0_1, P0_0}
set_port_is_pad {P1_7, P1_6, P1_5, P1_4, P1_3, P1_2, P1_1, P1_0}
set_port_is_pad {P2_7, P2_6, P2_5, P2_4, P2_3, P2_2, P2_1, P2_0}
set_port_is_pad {P3_7, P3_6, P3_5, P3_4, P3_3, P3_2, P3_1, P3_0}
set_port_is_pad {sfr_data ,rom_data, rom_addr}
set_port_is_pad {test_mode0, test_mode1, test_rd, test_wr, test_RW_dir}
set_port_is_pad {RST,PassCrystalFun,dma_req,addr_len,sel_xtal_ring}
set_port_is_pad {sfr_wr, sfr_rd, sfr_rw_dir, sfr_addr}
set_port_is_pad {rom_oe, load_ok, core_clk_out, fail_delay_out, ALE, MemoryMap}

set_pad_type -exact INPUT_PAD {test_mode0, test_mode1, test_rd, test_wr, test_RW_dir};
set_pad_type -exact INPUT_PAD {PassCrystalFun,dma_req,addr_len,sel_xtal_ring};
set_pad_type -exact INPUT_SCHM_PAD {RST}
set_pad_type -exact OUTPUT_PAD {sfr_wr, sfr_rd, sfr_rw_dir, sfr_addr};
set_pad_type -exact OUTPUT_PAD {rom_oe, load_ok, core_clk_out, fail_delay_out, ALE, MemoryMap};
set_pad_type -exact INOUT_PAD {sfr_data , rom_data, rom_addr}
set_pad_type -exact INOUT_PAD {P0_7, P0_6, P0_5, P0_4, P0_3, P0_2, P0_1, P0_0}
set_pad_type -exact PULLH_PAD {P1_7, P1_6, P1_5, P1_4, P1_3, P1_2, P1_1, P1_0}
set_pad_type -exact PULLH_PAD {P2_7, P2_6, P2_5, P2_4, P2_3, P2_2, P2_1, P2_0}
set_pad_type -exact PULLH_PAD {P3_7, P3_6, P3_5, P3_4, P3_3, P3_2, P3_1, P3_0}

insert_pads
compile -map_effort med -verify_effort low

 

[seasonyangd]

How to config library?

Thanks again. I have read the script that you past. But I think it just for add pad in DC. I have done like that. DC always say that "P2A" is not usable, it have no function. I think because of our I/O library need to be config to meet our need. How can I do?

 

[farmerwang]

Insert it manually

Do not automatically insert pad use DC, do it by yourself!!!

 

[ramo]

Insert pad use DC...do it by yourself...

All the best!!
Ramo :lol: :lol: :lol: