vimedu
Junior Member level 2
Hi guys
I have a sample verilog code and want to synthesize using Design Compilor. And also I want to add IO pads during synthesis.
Is it possible to do this? If possible , what is the procedure?
My inputs are clk, reset, SI and output is outready and PO[7:0]
Thanks in advance
I have a sample verilog code and want to synthesize using Design Compilor. And also I want to add IO pads during synthesis.
Is it possible to do this? If possible , what is the procedure?
My inputs are clk, reset, SI and output is outready and PO[7:0]
Thanks in advance