How to add bits of a std logic vector and result should be std logic vector

amit.kn said:

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Code VHDL - [expand]
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[syntax=verilog]

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[/syntax]


Dear All,

I have a VHDL code in which i am using a std_logic_vector i.e
code:= std_logic_vector(255 downto 0);

I want to add all the bits and store into a vector of 8 downto 0.

Example:

if code = "010101......................0101", suppose we have 90 1's in code then ans should be 90 and should be stored in one more logic vector which is 8 downto 0.




Best Regards
Amit kumar

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vipinlal said:

run a for loop to add all the bits.

But if you want a synthesisable design, a for loop will not work. In that case you have to do one addition per clock cycle. and you get the result after 256 clock cycles.

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