How this "j" of I+jQ is implemented in DSP/FPGA/uC

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jeeturivinod

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Queries about "j" parameter of complex numbers and I,Q

>> How this "j" of I+jQ is implemented in real hardware ? What is the equivalent of "j" in real hardware(DSP/FPGA)?

I can generate in phase component ( I ) and Quadrature component ( Q ), after this I have to multiply Q component with "j" and then add it with I.
As per theoritcal point "j = root(-1), but reality "root(-1) does not exist, then how can we implement actual complex number.

or My assumptions are wrong!...
is it something like "j" is never implemented,it's just name sake?

Actually why we need I, Q components?
 

if you use fft core(with xilinxs core generator) u will see two output. One of them is real part and the other one is imaginary part. So, if your output is (a + jb) it means two outputs. One of a and the others b. Anyhow, we dont use j number. We use j's coefficient. For phase tan(b/a), for magnitude root(a^2 + b^2). By the way sorry for my english...
 

Re: How this "j" of I+jQ is implemented in DSP/FPG

Hi Zula

Thanks for your response.

As per your answer I've another query..that is :
you have mentioned that we will use j's coefficient. In general what is the value range of j's coefficient and how do we generate j's coefficients ?

I will try FFT core of Xilinx to understand some more details.
 

we can compute e^(-jw) this way; e^(-jw) = cosw - jsinw.As u see j's coefficient is sinw. And there is many way for computation sinus and cosinus. One way is cordic algorithm.
 

Re: How this "j" of I+jQ is implemented in DSP/FPG

What is the equivalent of "j" in real hardware(DSP/FPGA)?
Click to expand...
I understand, that real hardware means real-time signal processing. In many cases, "j" simply means a 90° phase shift
of a signal. It's easy to perform for a single frequency or small bandwidth signal by adding a delay. For a wide band signal,
it involves a complex "Hilbert transformation" filter.
 

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