How the gate count of a design is determined?

[snr_vlsi]

Hi,

Can anyone tell me how the gate count of a design is determined.
what is gate density, placeable instances.

how is die area calculated?

thx
snr

 

[gliss]

design compiler gate count

A synthesis report will tell you the gate count.
Die area could be estimated from the synthesis report but I think it's better to get the die area after P&R.

 

[snr_vlsi]

equivalent gate count

We know that gates in a design are represented as 2 input Nand gate equivalents. Generally, the design comprises of standard cells and macros.

Now, in order to get to to know the gate count of a design. We generally multiply the no. of standard cells x 4. This is because any logic (and, or, exor, nor gates etc) in the design can be implemented with min. four standard cells. Is this correct?

Now, what is the term placeable instances mean? Does it comprise of macros and the no. of standard cells in the design.

What is gate density? Does this vary with technology and the process.

Now coming to the die size estimation,

generally 30% of the die area is allocated for macros and standard cells and 70% of the die area is assigned for routing.

Does anyone have any calculation ( clear explanation ) about die are estimation.

thx

snr

 

[ramanav]

what is gate count

Hi ,
Synthesis report gives total cell instances.
How to get gate count from them.

 

[NanhTrang]

gate count area

here's the equation:
gate count = Total area / area of NAND2 gate
So you got to run a simple nand2 gate to see it's area, then use the above formula

 

[master_picengineer]

nand gate area

here's the equation:
gate count = Total area / area of NAND2 gate
So you got to run a simple nand2 gate to see it's area, then use the above formula

Are you kidding ?

 

[hpinmax]

design compiler report_area

the above fomula is correct. there are several method to calculate it, even though I cannot remember all.
However, above fomula is one of them.

 

[master_picengineer]

design compiler + report_area

Great !
Where did you find it. I need badly to understand this. Is the any paper, refernce in that context to share ?

Thanks in advance.

 

[diag]

how to compute area from equivalent gate count

Because Design Compiler doesn't derive any area units, the number reported
by report_area is actually the sum of the area attribute attached to cells
in the technology library. Basically, you have to ask the vendor what the
area units mean. For example, some library vendors might define the area to
be (sqmm x sqmm) or normalized to the size of a 2-input NAND gate. That is,
a 2-input NAND gate has an area of 1.

 

[sam536]

gate count + number of instances

To get the equivalent gate area in Design compiler need to add two comamnds in TCl script.

1. First to get the total area of your design, use report_area.
2. Then divide this area by the area for a 2-input NAND gate in your technology library. You can also use the following command to find out the area for a 2-input nand gate.

dc_shell-xg-t> get_attribute { technology library/2_input_nand_gate_name } area

to get the 2_input_nand_gate_name, use report_lib <tecnology_lib > and select the any drive strength. Usually its 1x drive strength.

Area = $report_area/Area_of nand gate

Regards,
Sam

 

[vcnvcc]

I am asking this w.r.t. DC synthesis QoR report -

QoR report says all area Combo area & non combo area; along with that it also says Black box area.

Now my question is while calculating area for Die size estimation - DO I have to consider this black box area as well?

I think - I should take into consideration, but got confused as it is not PnR reports..

Can you please share your inputs...Thanks.