How signal integrity affects timing?

[vreddy]

SI

can anyone tell how the signal integrity effect timing??

thanks

 

[mkhan]

Re: SI

Hi,

SI effects the timing as follows :

Does the signal reach its destination when it is supposed to?
And also, when it gets there, is it in good condition?

In general, the goal of signal integrity analysis is to ensure reliable high-speed data
transmission. In a digital system, a signal is transmitted from one component to another in the form of logic 1 or 0, which is actually at certain reference voltage levels. At the input gate of a receiver, voltage above the reference value Vih is considered as logic high, while voltage below the reference value Vil is
considered as logic low.

I hope i explained the SI somehow.

In the E-books section i m uploading a chapter on SI and timing, u can downlaod from if u want more explanation.

BR,

Arif Khan
Please press helped me !!!

 

[shelby]

Re: SI

SI can effect the delay throught a net by either increasing its delay (effecting setup time) or decreasing its delay (effecting hold time).

Imagine a net with a weak driver (victim net) surrounded by nets with stronger drivers (aggressor nets). If all the nets switch from low to high around the same time, the aggressor nets can help pull the victim net high faster than normal, decreasing it's delay. If all aggressors are switching from low to high and victim is switching high to low, the aggressors can fight against the victim net making it harder for it to switch from high to low and increasing its delay.

How much effect an aggessor net can have on a victim is determined from the drive strength of its driving cell and the coupling capacitance between the two nets (which comes from the extraction tool and written out into the spef file).

Possible fixes for this include increasing victim net drive strength or increasing spacing between the victim and aggressor nets.